Switching Clock Sources

[Rochey]

I have 2 crystals (in HC49 smd packages)
One is:

22.5792 MHz
24.567 MHz

I'd like to be able to switch between them.

As far as I know, my options are:

Relay - old school, mechanical connection.
Electronics switch/mux

I like the idea of a relay, but I'm wondering what the effects of using a CMOS switch would be. Would it introduce jitter etc?

Cheers

R

 

[jdbakker]

[quote author="Rochey"]I have 2 crystals (in HC49 smd packages)[...] I'd like to be able to switch between them.[/quote]
No, you don't. Switching between crystals is possible, but it usually introduces so many parasitics that you only want to do it when (a) space is extremely tight or (b) your oscillator's active element is so expensive that you can only afford one for multiple frequencies. Usually it's better to build/buy an oscillator for each frequency of interest and switch the desired one into the circuit.

(If you must switch crystals, transistor or PIN/Schottky diode switches are likely the way to go. Have a look here for one possible solution).

[quote author="Rochey"]I like the idea of a relay, but I'm wondering what the effects of using a CMOS switch would be. Would it introduce jitter etc?[/quote]
Everything you add will increase jitter, if only through Johnson noise. How much added jitter can you tolerate?
How often will you be switching this? Once at power-up? Every second?
How concerned are you about what happens while switching between frequencies?
How large can it be? How power-hungry? How expensive?

JD 'you've got questions, we've got more questions' B.

 

[Svart]

How much jitter can you stand is a good question. You can use RF GAs switches if you can stand a little more jitter but you WILL have to move to clock oscillators instead of crystals.

If you do use crystals, JDB is (again) correct to suggest PIN diodes.

 

[clintrubber]

Switching oscillators: the ADA8k-schematics show this for instance (see the GDIY-gmail-account)

 

[jdbakker]

[quote author="clintrubber"]Switching oscillators: the ADA8k-schematics show this for instance[/quote]
...yes, but...

The ADA8k schematics shows a design which functions, and which is cheap to implement. I wouldn't say that it's the best you could do performance-wise (even without going for very expensive/esoteric techniques). Whether this matters depends on Rochey's wishes, of course.

JDB.
[one thing Uli&Co did get right is to not just deselect but stop clock oscillator A when osc B is selected. I would suggest doing something similar, possibly even removing power from the currently unused oscillator]

 

[clintrubber]

[quote author="jdbakker"][quote author="clintrubber"]Switching oscillators: the ADA8k-schematics show this for instance[/quote]
...yes, but...

The ADA8k schematics shows a design which functions, and which is cheap to implement. I wouldn't say that it's the best you could do performance-wise (even without going for very expensive/esoteric techniques). Whether this matters depends on Rochey's wishes, of course.[/quote]
True, was not meant as an example as the best way to do it. But hey, - in general - if it's cheap to implement that doesn't necessarily mean that can't be decent (or actually pretty good) for the task at hand ! :wink:

Even more so, I think it's more of an accomplishment to make something work well at near no-budget than to make it great without any budget-limitations - again, in general, not w.r.t. espec. the ADA8k specific in mind - although it might sure be a good candidate for a pretty-nice-box-at-low-price example (OK, let's ignore the power-supply issue)

one thing Uli&Co did get right is to not just deselect but stop clock oscillator A when osc B is selected. I would suggest doing something similar, possibly even removing power from the currently unused oscillator

Removing the power might be overkill - stopped is stopped; the inhibited combination of inverter & Xtal won't be a zombie that tries to get going again.

Apart from that, the Xtal+single inverter topology is (despite that it's widely used) not the most desirable way to realize an Xtal-oscillator. Although I can't back this up with hard facts now, I guess improving on that might be the most important direction for eventual mods.

Bye,

Peter

 

[jdbakker]

[quote author="clintrubber"]Even more so, I think it's more of an accomplishment to make something work well at near no-budget than to make it great without any budget-limitations[/quote]
Absolutely agreed.

[quote author="clintrubber"][quote author="jdbakker"]one thing Uli&Co did get right is to not just deselect but stop clock oscillator A when osc B is selected. I would suggest doing something similar, possibly even removing power from the currently unused oscillator[/quote]
Removing the power might be overkill - stopped is stopped; the inhibited combination of inverter & Xtal won't be a zombie that tries to get going again.[/quote]
No, but a logic gate oscillator which is stopped by pulling its input low is somewhat more likely to start slowly or in a different mode (->frequency) than one which has its power removed and re-applied, especially if the latter happens with a fast enough slew rate.

[quote author="clintrubber"]Apart from that, the Xtal+single inverter topology is (despite that it's widely used) not the most desirable way to realize an Xtal-oscillator. Although I can't back this up with hard facts now, I guess improving on that might be the most important direction for eventual mods.[/quote]
Oh yes. Logic gates don't make good oscillators for several reasons, including:

- for a stable low-noise oscillator you want to have just enough loop gain to sustain oscillation. Logic gates tend to have buckets of loop gain, with no simple way to AGC.

- for a stable low-noise oscillator you want to have a low-noise active element. Logic gates, while not extremely noisy, are certainly not optimized for noise performance.

- while any low-noise oscillator circuit really needs to have a good, filtered supply, PSRR in the active element helps too. A logic gate only has 6dB PSRR at mid-supply.

This Linear Tech AppNote (which I may have linked to before) has more interesting stuff on clocks and oscillators.

JDB.
[not that I believe the gate oscs are the worst offense in the ADA8k's clocking circuit. That particular award goes to the WC-input: it first PLLs the WC up to 256Fs, and then immediately divides it by 256... Fixing this would have cost an extra chip, at ~$0.05 in Uli quantities (plus routing, plus board real estate, plus higher P&P cost, I know...)]