Deltalab Effectron voltage rails question

[pvision]

Well done getting that psu to fit. To my knowledge, all the Effectrons are very similar with more memory in some. The really early ADM64s, etc, don't have some of the CMOS switching of the others but from the 1024 onwards they share a lot of circuitry. The Super Time Lines have a different setup with the Delay Factor pot using the second part of the travel of the pot to control an envelope trigger

 

[TVC15]

Thanks for that clarification. I have been struggling with deciphering some of the CMOS switching from this mildly infuriating schematic.
I have never seen it drawn like this. For example, below in the upper left, those two logic blocks appear to be numbered U58 which is a CD4053. But another logic block is drawn in front of U52 which does not appear to be labeled but seems to be also part of U58.
Additionally, if anyone can explain to me how the ADC and DAC is achieved in this unit, I would appreciate it.

 

[JohnRoberts]

Additionally, if anyone can explain to me how the ADC and DAC is achieved in this unit, I would appreciate it.

Delta modulation A/D conversion is pretty simple... At the simplest you have an integrator that is alternately charging up during digital one, and discharging down during digital zero. A fast voltage comparator (like the 311) compares the incoming audio to the output of that charging up/down capacitor. The comparator outputs a one or a zero every clock tick based on whether the audio signal is below the charging cap and needs to keep going up resulting in a one output, or is higher so needs to start discharging down resulting in a zero output. The digital output is a string of ones and zeros.

The D/A convertor just reverses the process feeding the series of digital ones and zeros into another up/down capacitor integrator.

There are variants on the simple up/down delta modulation convertor where multiple clock ticks of all ones or all zeros generate a steeper slope up/down. Despite the simplicity, the fidelity of delta modulation can be quite good if the sample frequency is high enough. To do that requires lots of memory that was very expensive back when these were manufactured so long delays may involve lower sample frequencies than would deliver good fidelity.

JR

 

[TVC15]

Thank you, John, for that explanation.
So would it be accurate to say that U5, U6, and U7 comprise the ADC and that the reverse process is carried out by U54, U55, U57 and U56?

 

[JohnRoberts]

Thank you, John, for that explanation.
So would it be accurate to say that U5, U6, and U7 comprise the ADC and that the reverse process is carried out by U54, U55, U57 and U56?

sorry I can't read those device markings in the schematic.

You mention a LM311 in an earlier post, that would most likely be the high speed comparator used in the A/D section. The D/A does not use a comparator.

JR

 

[TVC15]

No problem, the schematic is pretty bad.
My basic interpretation is this:
U5 (comparator) outputs to Data In of one half of a 4013 flip flop, (U6 -nearly invisible on the schematic) which outputs to a buffer to Data in of the RAM chips (as well as going to U7 which is a 4 bit shift register)
on the other end: Q out from RAM chips enters U54, which is another 4013 flip flop, which outputs to another 4 bit shift register (U55) as well as a 4016 analog switch (U57) and exits that switch into a 4558 op amp (U56) which feeds the feedback circuit and the output section.
I am curious how the shift registers are being utilized here.

 

[JohnRoberts]

No problem, the schematic is pretty bad.
My basic interpretation is this:
U5 (comparator) outputs to Data In of one half of a 4013 flip flop, (U6 -nearly invisible on the schematic) which outputs to a buffer to Data in of the RAM chips (as well as going to U7 which is a 4 bit shift register)

The 4013 is basically a one bit D type (data type) shift register. For the A/D conversion the 4013 latches the state of the high speed comparator when clocked.

on the other end: Q out from RAM chips enters U54, which is another 4013 flip flop, which outputs to another 4 bit shift register (U55) as well as a 4016 analog switch (U57) and exits that switch into a 4558 op amp (U56) which feeds the feedback circuit and the output section.
I am curious how the shift registers are being utilized here.

The 4 bit shift register may be used to generate a faster up/down ramp if sequential data does not change state. For example 4 ones in a row will slew up/down faster than 2 and 2... A similar circuit is used on the D/A end so output tracks input.

JR

 

[pvision]

I have a collection of schematics & etc on my website:

https://www.bn1studio.co.uk/hail-the-effectron/

 

[JohnRoberts]

Deltalab (Richard DeFreitas... RIP 2019) won the "bang for the buck" competition for inexpensive studio delays back in the 70s/80s. They spanked my (LOFT) BBD analog shift register based delays. Digital memory was pretty expensive back then so the sound quality could get grainy at longer delays when using lower clock frequencies.

JR

 

[TVC15]

pvision - Your website is where I got the schematic I'm using, it's the one marked as the Super Time Line. As you mentioned it is almost identical. I appreciate your effort in pasting all those scans together.

John- at least yours had a power button, and no battery to explode. This thing probably wouldn't be so riddled with faults if it had been turned off once in awhile.

Definitely needs a new comparator. Dry signal also getting lost somewhere before the output section. More bad chips to pull. Total basketcase, but Oh so much fun!

 

[pvision]

I thought the schematic looked familiar!

I have an embarrassingly large pile of broken Effectrons - and a similarly embarrassing lack of knowledge / experience in fixing kit like this!

My experience is that the analog section always seems to work but the delay signal goes awol somewhere along the line

 

[JohnRoberts]

I thought the schematic looked familiar!

I have an embarrassingly large pile of broken Effectrons - and a similarly embarrassing lack of knowledge / experience in fixing kit like this!

My experience is that the analog section always seems to work but the delay signal goes awol somewhere along the line

The digital section is basically a one bit shift register with multiple old memory chips in series. The digital signature of the deltamodulation bit stream is pretty recognizable, so look for when it stops coming out of the memory chips upstream from it. Digital memory addressing is not trivial but fairly straightforward. I wouldn't be surprised if some of those old digital memory chips are getting harder to find.

JE

 

[TVC15]

I did some work on this today... put in a new comparator in U5 - signal now goes through the encoder and into the RAM and out of the decoder, and I replaced another bad 4558 in U56 and that regained the main ouput but I'm not getting any effected signal at the output. The dry signal does not change at all through the full rotation of the delay mix pot.
I think I'm losing it at U8 (another 4558) - I have output from one half of U8 at pin 7 but nothing from pin 1. U8 could certainly be bad since I'm up to 3 bad 4558's in this unit so far. Pin 1 from U8 goes to the section with the delay factor control and modulation ,, although I don't understand how that section is supposed to work - what happens to the signal from U8 pin 1, and how do the Column Address Strobe and Row Address Strobe factor in.
I found a clearer version of the schematic and have marked the path from U8 to the delay/modulation area in red if anyone could shed some light on the theory of operation here.

 

[JohnRoberts]

You should find the digital pattern of ones and zeros coming from the encoder. That digital signal then needs to travel through multiple RAM delay chips one at a time.

[edit] Troubleshooting digital is different from analog. With deltamod the encoder and decoders are mostly analog.

As I said before the is a one bit (zero or one) data stream coming from the encoder that must pass through all the memory chips in series and emerge unchanged.

For the memory to work you need several component glue circuits working together.

#1 there needs to be a master clock... (note: the encoder would not work without the master clock so I ASSume the clock is working. ) The clock period/frequency is adjustable to vary the delay time.

#2 the memory chips require suitable addressing. The series of sequential addresses is typically generated from clocking a counter (or multiple counter in series).

#3 RAM chips are particular about read/write strobing

To trouble shoot, you have already confirmed that the encoder and clock is working.
-next I would confirm that delay control is varying the clock frequency
-next look for a suitable memory address cycling
-check if one bit data stream is coming out of the first memory chip, then the next.

Caveat... this is easier to write than to do... [/edit]

====

Look at a data sheet for the specific memory chips used in that delay to see what kind of clock, and address lines it needs. The address lines are usually generated with a counter.

Good luck

JR

 

[TVC15]

Thank you for your help, John.
the Memory chips are MK4564 - looking at the datasheet I see that the chips needs two clock signals; one for RAS / one for CAS
Should I then see clock on the pins for RAS and CAS, and that frequency should be affected by the delay factor pot / delay time switches?
the LFO section works and I was able to vary it's pulse width and speed, but it has no effect on the ouput, although I have not actually seen it modulating the master clock. I confess to having a hard time identifying the source of the master clock in this circuit - though I suspect it is in the section I outlined in the schematic in the previous post.
Would you please elaborate on what suitable address cycling should look like? The circuit uses 4 x 40193 counters - should I see clocking on the count up / count down pins?
I should clarify that when I said the dry signal does not change through the rotation of the mix pot - that's not really correct... when I ran audio other than a sine wave through it, I could hear the phase shift as I rotated the pot from 100% wet in phase to 100% dry and to -100% wet out of phase - so I have the full output from the decoder at 100% wet but it's not delayed.

 

[JohnRoberts]

When troubleshooting a design that was working before, rather than dissecting the design minutiae, first look for something simple that is faulty. The digital bit stream has to pass through multiple RAM chips in series. If even one of the several memory chips is bad, the digital bit stream will not make it all the way through.

In fact a bad memory chip could interfere with the address lines that are all bused together.

I am just spit balling here, I know in general how they work but I have never had one on my bench to fix.

JR