Help me MOD - D&R FET STEREO limiter

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I made GREAT progress yesterday. I made bunch of different mods, that worked (surprisingly) as expected and shown in LTspice model.
Most of them worked functionally as expected, but some were less musical and useful then others.

I tried relaxing the ratio with R27/R57 with 100k pot.
Increasing the threshold with R8/R41 with 10k instead of 20k resistor.
Bypassing diode D6 for for faster release action. worth it
Adding 1K pot after R22 resistor for fine tuning of the attack.
Replaced R6/R50 22K with a 100K resistor, for greater amplification factor of the main gain cell. worth it

The way I see it its fixed threshold design, and the threshold knob is actually input attenuator. The first gain stage (opamp + fet) work in sort of unity gain, when no compression is present. The most useful mod I did is replaced R6/R50 22K with a 100K resistor (also bypassing the diode D6). This by default amplifies the signal more and allows to drive the FET and side-chain harder. You still have input attenuator and output gain, so you still have all the subtle compression of the original design if needed, but you know have option to compress the shit out of drums.

The main problem with this design is ugly noncontinuous shape of attack. It create ugly spit/thump transients, that are very unmusical when you try to use slower attack times, for more subtle applications. It basically sounds shit when the attack is slower than instant. It does not create slower attack, it basically delays the attack that is still fast.

And you can even see it in LTspice simulations:

fast D&R attack (good)
1704963599766.png



slow D&R attack ( basically delays the attack that is still fast.)
1704963546258.png




In comparison with gSSL LTspice model that has "pretty" attack curves:

fast SSL attack
1704963913053.png



slow SSL attack

1704964104099.png



@gyraf @richiyobs @JohnRoberts Is there any way of reshaping the sidechain to make attack more "log/exp" shaped or is this just a inherent property of a FET design?
 
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@gyraf @richiyobs @JohnRoberts Is there any way of reshaping the sidechain to make attack more "log/exp" shaped or is this just a inherent property of a FET design?
I am not sure what exactly you are asking for. I didn't follow this entire thread but quickly scanned it. I suspect your results are more dominated by feedback topology, rather than the specific gain element used.

Back in the 70s/80s I spent many bench hours messing with dynamic processing, mostly for companding noise reductions. I built a special tone burst circuit that allowed me to gate a tone on/off while adding back in a steady state signal to study attack/release behavior in more like real world conditions but actually harder than in real life. In fact I was able to run complex audio through my tone burst circuit to punch up the dynamic content (crest factor) of regular music to make it harder for dynamic processing.

I would also caution against investing too much effort into how it looks on a scope and instead focus more on how it sounds. They are not always the same. 🤔 FWIW back when I was designing companding noise reductions my design goal was to be as transparent as possible without spurious audible artifacts. There are multiple moving parts in dynamics processing so don't expect to find simple answers.

Analog dynamics processing is a mature field, so identify a processor that you like the sound of, then seek to understand the entire design. Warning there will likely be subtle factors that are not immediately obvious.

JR
 
After altering to 100k the feedback resistor at jfet amp ... Have you tried to disconnect the jfet from signal Path to check its level? Any distortion?
Or simply disconnect sidechain....
The gain of that amp Is fine... Is 1dB less respect to incoming signal if you bypass sidechain

The Thr amp Is to beat harder the sidechain i believe ... Keep signal Path as It Is... You can also Better measure compression....as J.Roberts said It s feedback One so you can try to feed sidechain from input signal ... The Level Will be higher respect to the original config where mV are sent to thr amp
 
simulated with 100k at jfet amp , signal goes up to 3v respect to 600mv of the original, so no ditortion....

cheers

Edit- in SIM the input pot was not at minimum value... But sending 1.228v you re still out of distortion
 
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