Greetings,
I have been struggling to understand how the attached attack & release circuit from design note 115 by THAT Corp. is actually supposed to to work. The design seems to assume that the comparator at the input swings low when the compression kicks in, and the constant current sources that are mirrored then discharge the timing cap. When the compression releases and the input signal goes back up to 0, the upper current mirror charges the cap back up.
This works as advertised in LTSpice. However, in the prototype, the comparator output is stuck at V+, and the output of the circuit hangs around -10V. I fail to understand how a comparator could ever have an output voltage of 0, or basically anything other than (near) V+ or V-. Is there something special about how the 393 is used here that I am missing?
Thanks for any insights or suggestions on how to think about this.
- Bertu
I have been struggling to understand how the attached attack & release circuit from design note 115 by THAT Corp. is actually supposed to to work. The design seems to assume that the comparator at the input swings low when the compression kicks in, and the constant current sources that are mirrored then discharge the timing cap. When the compression releases and the input signal goes back up to 0, the upper current mirror charges the cap back up.
This works as advertised in LTSpice. However, in the prototype, the comparator output is stuck at V+, and the output of the circuit hangs around -10V. I fail to understand how a comparator could ever have an output voltage of 0, or basically anything other than (near) V+ or V-. Is there something special about how the 393 is used here that I am missing?
Thanks for any insights or suggestions on how to think about this.
- Bertu