sbeach
Active member
I want to be certain about this.
In the image, is the bottom 3-D pinout pic correct? In looking at the Toshiba spec. sheet (upper two images), in the 2nd pic, are you viewing the JFET from the top or the bottom? It SEEMS to be a bottom view. If so then the source & drain would be reversed compared with the bottom 3-D pic. I'm too confused. Please help me figure this out. Thanks.
In the image, is the bottom 3-D pinout pic correct? In looking at the Toshiba spec. sheet (upper two images), in the 2nd pic, are you viewing the JFET from the top or the bottom? It SEEMS to be a bottom view. If so then the source & drain would be reversed compared with the bottom 3-D pic. I'm too confused. Please help me figure this out. Thanks.