Boss DSD-2 Digital Sampler Delay

Bo Deadly · Sep 13, 2018

Regarding this Boss DSD-2 Digital Delay pedal schematic:

It seems the DAC (RA1) out goes through a buffer (6), through some analog gates (4abcd) and out. But it also goes down to the comparator (5) which is being used as an ADC? Why is the output mixing with the input?

I have another piece of gear I'm trying to fix (see other thead in The Lab) that uses the same chip (RDD63H101) so I'm just trying to understand how this works.

abbey road d enfer · Dec 17, 2018

squarewave said:
Regarding this Boss DSD-2 Digital Delay pedal schematic:

It seems the DAC (RA1) out goes through a buffer (6), through some analog gates (4abcd) and out. But it also goes down to the comparator (5) which is being used as an ADC? Why is the output mixing with the input?

I have another piece of gear I'm trying to fix (see other thead in The Lab) that uses the same chip (RDD63H101) so I'm just trying to understand how this works.

My understanding is that the comparator is just a part of the A/D and D/A conversion. I surmise the output of the DAC is compared to the input signal and provides a count stop to the SAR (successive approximation register). That was the technique prevalent before Sigma/Delta.

JohnRoberts · Dec 17, 2018

abbey road d enfer said:
My understanding is that the comparator is just a part of the A/D and D/A conversion. I surmise the output of the DAC is compared to the input signal and provides a count stop to the SAR (successive approximation register). That was the technique prevalent before Sigma/Delta.

+1 crude A/D with resistor array to make a cheap D/A, google "successive approximation". In addition to that looks like 2;1 companding (ne570) to improve S/N, and HF pre-de/emphasis to further improve perceived S/N.

Mixing output to input is likely part of effect (recirculation).

JR

Bo Deadly · Dec 17, 2018

I thought I found out what that was doing but this post is so old I don't remember.

It's not feedback. Feedback is in the upper right.

My best guess at the moment is that it makes the single NJM311D comparator ADC more accurate or less susceptible to clock noise or something. The comparator is comparing the input with the delayed output.

Weird. But that's why I asked. Some of these old pedal schematics have clever bits.

abbey road d enfer · Dec 17, 2018

squarewave said:
My best guess at the moment is that it makes the single NJM311D comparator ADC more accurate or less susceptible to clock noise or something. The comparator is comparing the input with the delayed output.

No. I already gave you the explanation. During the A/D conversion, the SAR register scans all the binary values and when the output of the DAC exceeds the actual sampled input signal, the comparator stops the SAR counter. It's not comparing with the delayed signal. That was the standard when ADC chips were expensive.

Bo Deadly · Dec 17, 2018

abbey road d enfer said:
No. I already gave you the explanation. During the A/D conversion, the SAR register scans all the binary values and when the output of the DAC exceeds the actual sampled input signal, the comparator stops the SAR counter. It's not comparing with the delayed signal. That was the standard when ADC chips were expensive.

I see. So the the SAH pin turns off the analog switches so that the DAC can be used to sample the input by stepping through and testing each bit. Then it flips the gates open and uses the DAC to output the delayed signal and prime the input for reading the next input sample. So the DAC is doing double duty alternating between outputting the signal and outputting bits to compare with the input.

JohnRoberts · Dec 17, 2018

squarewave said:
I see. So the the SAH pin turns off the analog switches so that the DAC can be used to sample the input by stepping through and testing each bit. Then it flips the gates open and uses the DAC to output the delayed signal and prime the input for reading the next input sample. So the DAC is doing double duty alternating between outputting the signal and outputting bits to compare with the input.

This (SAR) is pretty old (digital) technology. You drive a D/A starting with the most significant bit, and compare the output of the D/A to input for above/below after each step... The trouble is it takes as many comparison steps as bits, but was the "best way" back when.

JR

abbey road d enfer · Dec 18, 2018

squarewave said:
I see. So the the SAH pin turns off the analog switches so that the DAC can be used to sample the input by stepping through and testing each bit. Then it flips the gates open and uses the DAC to output the delayed signal and prime the input for reading the next input sample. So the DAC is doing double duty alternating between outputting the signal and outputting bits to compare with the input.

Right.

Boss DSD-2 Digital Sampler Delay

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