Hi Samuel,
[quote author="Samuel Groner"]I forgot to mention that you could parallel a few BC560Cs to get a closer match with respect to rbb' and capacity.[/quote]
That'll help (550C). Will also see if I can hack the model to tweak for lower rbb'.
Basically there is little reason to believe that simulation is inherently inaccurate for low-noise design. But both DC precision and noise behaviour depend heavily on ill-defined and widely variable parameters such as rbb'/hFE/Vbe and may show a dependence on difficult (not usually impossible, just tedious) to simulate parameters such as thermal effects and PSU or ground limitations.
No indeed, actually I should have phrased that differently - I was more thinking about inaccurate model-parameters, like you added. Sim-results never better than the accuracy of the relevant parameters.
One of the thing I want to toy with is the influence on noise-performance of hFE- & Vbe-variations. As in: for a low-gain balanced circuit the DC-offset doesn't matter to much to me, but without getting the equations out yet, the question came up as to what would be the best property to match BJTs for: hFE or Vbe.
Equations & pencil & paper will tell more, but so far for noise-performance I'd at first vote for hFE-matching over Vbe-matching (despite it turns up as sqrt(hFE)), but a delta-Vbe will give a delta-Ic which spoils the optimum value again (hFE & Rsrc --> Ic_opt).
And can't rely on any correlation in both spreads (hFE & Vbe).
Not unlikely though the hard resulting performance figures will tell it's mostly academic, since the 'OSI-optimum' isn't too sharp, so vv for Ic.
Simply build, I might perhaps better skip the sim-phase and just measure resulting performance for a few different BJTs with known hFE & Vbe.....
IC manufacturers surely have all the data for their processes though.
Yes :grin: and no...
the places to fit the parameters are all there (= the models can handle them), but unfortunately not all processes yet fully characterized once designers need to start making first designs in them. That may be temporarily for most processes (...), but in the past some CMOS-processes remained lacking w.r.t. full analog characterisation of devices (espec. for sub-threshold: models can handle that region, but no accurate parameters).
Now that we're approaching the point of CMOS with just-above zero supply voltages, about any analog sign of life could be considered compromised :wink: , so luckily the need for proper characterisation has been better recognized.
In the end you have to understand both circuit and simulator yourself to estimate the validity of the results. In that particular case you mostly need to know that using higher-rbb' and -fT models may lead to unrealistic stability margins for high feedback designs.
Luckily the simple stage I mentioned earlier does local feedback, no global, so that'll help here I assume for now, but otherwise indeed trouble of inacc. stability validity.
I never used noise simulation as noise performance (within the audio band) can be pretty easily estimated by hand (read: Excel/Matlab) calculations using standard approaches--I see that you allready got a copy of the relevant book.
You spotted it :wink:
I think it was Brad/bcarso that I saw first mentioning it and after some more appearances it was clear this was a nice book to have :thumb:
Regards,
Peter
