(Basic) Clock-Questions to the ADA8000-Section.

[wilma]

Hi guys,

I'd like to build a neat compact A/D-Converter with ADAT out based on the Wavefront pair AL1101 (A/D) / AL1401 (OPTOGEN), as used by Behringer in the ADA8000. I have disassembled an ADA8000 and looked at the schematics to it, to get everything right. I have experiences with analogue preamp sections and I'm aware of the function from A/D, but it's the first time for me to (re)build somthing with a clock distribution. So there are some questions to it:

This device (as many others) has four clock operations:

1. Master 44.1kHz (derived from the first internal XTAL with 11,2896MHz, labeled "CLK11")
2. Master 48kHz (derived from the 2nd internal XTAL with 12,288MHz, labeled "CLK12")
3. Slave ADAT IN (output from the AL1402 with internal PLL is labeled "OPTCLK", the sync lock-indication, lowactive, is labeled "OPTLOCK")
4. Slave Wordclock IN (output from the PLL (?) 4046 is labeled "PLLCLK", the sync lock-indication, lowactive, is labeled "PLLLOCK")

So far, so good.

All CLK-Signals lead to an 74HC153 @ "MUXB", pin 10-13 (CLK11 / CLK12 / OPTCLK / PLLCLK). The Sync-lock-indications lead to the same chip @ "MUXB", pin 5+6, 3+4 clamped to 5V. There are two signals from the clock-operation switch to that chip, "SELA" & "SELB", that are lowactive when Slave-wordclock or slave-ADAT is selected, that makes sense.

My questions aim to what happens on the outside of the 74HC153:
- @2Y, output of MUXB are two 74HC393 in series. The 2nd outputs the CLK-Signal "ULRCLK".
But: CLK11 & CLK12 are in MHz range and OPTCLK / PLLCLK are 44.1/48kHz, right? Don't the two 74HC393 divide the 256x fs MHz-Signals down to 1x fs? Aren't then the 44.1kHz / 48kHz Signals then divided down, too?

- @1Y, output of MUXA is the Signal "CLKLOCK".
- ULRCLK runs through two schmitt triggers (74HC132) in series, the first is bound to the CLKLOCK Signal from 1Y, the output is "LRCLK"
So, with the PLL-function: ULRCLK is distributed to the 4046 (for WC IN) and the AG1402 (ADATIN) as the reference-signal, because the aim is to resync the external CLK to the received data, but ULRCLK is derived from PLLCLK (in case of WC IN is active), so the only phase shift to be compensated is the one generated from the 74HC153 and the two 74HC393 in series, or not?

Then another thing: in my A/D-Project, there won't be an OPTOREC (AL1402). In the schematic of the ADA8000 the OPTLOCK-Signal from it is used to unlock the schmitt-triggers to distribute the internal clocks CLK11 and CLK12, too, although they don't have to be checked, if they're synchronised to anything, is that right? So, if there isn't any AL1402 in my plans, isn't is just possible to switch a "lock"-indicator with the switch that sets clock-operation (WC IN-option is in my project, so the schmitt triggers blocking unlocked signals make sense)?

Am I right, or far out?

Greetz,

wilma

 

[jdbakker]

Welcome.

- @2Y, output of MUXB are two 74HC393 in series. The 2nd outputs the CLK-Signal "ULRCLK".
But: CLK11 & CLK12 are in MHz range and OPTCLK / PLLCLK are 44.1/48kHz, right?

No. OPTCLK, from the DVCO pin of the AL1402, runs at 256*Fs; similarly the 4046 VCO/PLL combo produces a MHz-range clock on PLLCLK.

- ULRCLK runs through two schmitt triggers (74HC132) in series, the first is bound to the CLKLOCK Signal from 1Y, the output is "LRCLK"
So, with the PLL-function: ULRCLK is distributed to the 4046 (for WC IN) and the AG1402 (ADATIN) as the reference-signal, because the aim is to resync the external CLK to the received data, but ULRCLK is derived from PLLCLK (in case of WC IN is active), so the only phase shift to be compensated is the one generated from the 74HC153 and the two 74HC393 in series, or not?

Not even that; the PLL locks to the phase on CIN, which is the ULRCLK signal. As the 74HC153 and the two 74HC393 are inside the PLL feedback loop any phase lag they introduce is automatically tuned out.

(There is no fundamental reason why the 4046 PLL has to run at 11+MHz. It could have run at Fs ((44-48kHz), eliminating the 393 from that loop, but that would have made the selector logic more complex/expensive)

Then another thing: in my A/D-Project, there won't be an OPTOREC (AL1402). In the schematic of the ADA8000 the OPTLOCK-Signal from it is used to unlock the schmitt-triggers to distribute the internal clocks CLK11 and CLK12, too, although they don't have to be checked, if they're synchronised to anything, is that right? So, if there isn't any AL1402 in my plans, isn't is just possible to switch a "lock"-indicator with the switch that sets clock-operation (WC IN-option is in my project, so the schmitt triggers blocking unlocked signals make sense)?

If you follow the decoder logic you'll see that OPTLOCK is only used to enable the ULRCLK-to-LRCLK clock gate if ADAT is selected as clock master. Without an AL1402 you won't have ADAT clocking as an option anyway, so you might as well tie OPTLOCK high and have a three-position clock source switch (44k1/48k/WC) instead of the four-position switch the ADA8000 uses.

By the way, have you seen rkn80's modular multi-channel converter project?

JDB.

 

[wilma]

...Dope!

@JDB: You simply rule  8) Thank you!

BTW: I was gonna measure the output of our WordClock in our Studio (LakePeople, I think), just to check what fs the output is. Did I miss sth. and transmitting 256xfs is usual (I see - better is better, but I never ran into it until now)?

I will have a look @ the project you linked, big thanks!

Greetz,

Wilma

 

[jdbakker]

Did I miss sth. and transmitting 256xfs is usual (I see - better is better, but I never ran into it until now)?

No, Word Clock (WC) typically runs at fs. There are all kinds of proprietary clocking methods (like SuperClock) that run at higher rates.

Like I said, the 4046 PLL locks its internal 11+MHz VCO to the incoming 44-48kHz WC. The two 393s form the N-divider in the feedback loop. Have a look at basic PLL theory for the big picture.

JDB.

 

[Val_r]

In that ADA8000 schematic, are the two 393 in series forming a 256x divider?
So is the PLLCLK set at 11.2896MHz?

 

[tomcat]

Somebody has a link to a complete ADA8000 shematic?

 

[truzz]

The two 393s form the N-divider in the feedback loop. Have a look at basic PLL theory for the big picture.

JDB.

so the actual ADA8000 divider network is a 256x.
Is it possible to modify that for a divide-by-384 network?
What do you add?

 

[jdbakker]

Is it possible to modify that for a divide-by-384 network?
What do you add?

You would need to replace one of the /16 stages by a /24 stage, probably most easily realized by a /3 followed by a /8 or /12 + /2. Possible building blocks include the 74HC4059 and the 74LS92.

Why would you want to do this? Are you trying to run it at 32ksps?

JDB.