buffering the VAS

[mikep]

in a standard 3-stage op amp... as in the 990, etc. a BJT emitter follower can be used to buffer the common emitter VAS base current. What about using a FET source follower for this purpose? seems to me that it would better isolate the VAS base current from the diff amp. but all other things equal, a quick simulation shows significantly higher open loop distortion compared to a BJT, such results probably mean nothing, I still think it may be a good idea. any thoughts on the subject?


mike p

 

[bcarso]

Conjecture at least two things: (1) the potential required to bias the (assumed J)FET properly may choke off the (assumed) current mirror stage before, (2) the Cdg capacitance modulation may be substantially greater with the FET compared to the bipolar.

I'll do a little more pondering and maybe model when I get a chance.

 

[bcarso]

Additional thoughts: Self argues IIRC for the beneficial distortion-reducing local feedback effects of the pole-splitting capacitor wrapped around the bipolar buffered VAS.

Even with biasing adjusted to permit clearance of the current mirror's output collector voltage, which will remove some output voltage swing range, the transconductance of the JFET proposed is likely lower than a bipolar emitter follower, hence less loop gain of the stage with the pole splitting cap. Also typically capacitances will be higher, reducing loop gain at higher frequencies.

There's probably an arrangement with an additional device that would recover some transconductance in the composite VAS stage using the FET, although it would also contribute some more parasitic HF poles and need more compensation.

If there were a good low capacitance enhancement-mode DMOS part, something smaller than a 2N7000--BS170 class device, it might make the biasing at least a lot easier. Maybe even one of those would work, although you need to put a lot of current through it to get good gm. Note that these parts would require that the input stage be PNP rather than the typical NPN diff pair. Actually this would be a good idea even with the JFET since silicon P-channel FETs of either variety are of notably lower performance than N-channel.

 

[mikep]

Thanks for the insight. I thought capacitance might be a problem. I was thinking about the ALD zero-threshold devices for this application.

[quote author="bcarso"] Note that these parts would require that the input stage be PNP rather than the typical NPN diff pair. Actually this would be a good idea even with the JFET since silicon P-channel FETs of either variety are of notably lower performance than N-channel.[/quote]

This design I'm kicking around actually has an NPN input diff pair, NPN buffer (instead of the usual PNP) and PNP VAS. I wanted a bigger value resistor in the VAS transistor emitter (for another reason all together), and this seems to do it. It would limit swing, but Ive got a cascode eating a few volts of headroom on the positive side anyway. hmm.

edit: I believe the only drawback is you can't put a diode in parallel with the pole splitting cap to improve overload recovery, ala 990.

mike p

 

[bcarso]

I'll be interested in your results with the ALD parts, as I haven't played with those as yet.

 

[Samuel Groner]

Upon studying the DC balance of the input pair you will realise that the standard two-transistor current mirror used as the collector load of the input pair has significant base current errors. These are partially cancelled by the VAS base current error; if you use a FET for this the cancellation will not happen, increasing the DC imbalance of the input pair. I guess this is another important distortion contribution, but who nows without really looking at your design (and: never trust SPICE with respect to distortion once it gets below -80 dB).

Instead of the FET I rather suggest the use of another current mirror. See the LM741.pdf datasheet. By equalling the collector current of Q7 and Q15 the error contributions cancel and the input pair balance will be essentially perfect with matched transistors, without any disadvantages from using a FET.

BTW, the title of this thread is somewhat misleading I think; buffering the VAS rather implies a means to reduce the loading of the high impedance output node due to the output stage and not a beta-enhancement method for the VAS (which the discussed darlington connection actually is).

Samuel

 

[mikep]

[quote author="Samuel Groner"]the standard two-transistor current mirror used as the collector load of the input pair has significant base current errors. These are partially cancelled by the VAS base current error[/quote]

of course, this is one way to go. Brokaw gives a nice treatment of this in Williams' "Analog Circuit Design" book. He points out several weaknesses which I assume you know about.

But sometimes I assume too much! So to be more explicit: I am using a 4-transistor wilson mirror (made from 2x BCV62C)

I know the title of the thread is imperfect. but this isnt really a Darlington configuration either. 2 transistors, first connected common collector, the second common emitter, how is that darlington? It does enhance the beta of the VAS, but it also reduces the effects of the VAS base current on the diff stage, no? (and not just the DC component of the base current). That is what I am focused on, having been looking at the simulated open loop distortion of these types of circuits.

[quote author="Samuel Groner"] never trust SPICE with respect to distortion once it gets below -80 dB).[/quote]

I agree, but not completely. in an absolute sense, you are right. but when comparing different topologies using the same device models, I think relative differences shown in spice are worth consideration, even if they are improbable in their scale. When something sims with distortion at -140dBc it probably means "perfect" matching is at play, lack of parasitics, over-simplified device models, lack of self-heating (thermals) etc. but it is not a weakness of the software per say, the interpretation just needs adjusting. it is easy to delibrately upset the balance (in a number of ways) and see what happens.

 

[Samuel Groner]

Can you post a schematic? The devil lies in the detail, especially with the FET bias and the Wilson mirror.

2 transistors, first connected common collector, the second common emitter, how is that darlington?

You can re-route the collector of the common collector transistor to the collector of the common emitter transistor without any significant change in functionality or performance.

But when comparing different topologies using the same device models, I think relative differences shown in SPICE are worth consideration, even if they are improbable in their scale.

The problem is that there is not just a scale error but unadressed distortion sources (too many to be listed, say thermal distortion first). If you have one design at -140 dB and the other at -145 dB there is absolutely no guarantee that the later will be better than the former in real world. In fact the first might be accurately simulated as the un-SPICED distortion sources are negligible while for the latter they aren't. So real world might show -140 dB and -135 dB for the hypothetical designs.

Samuel

 

[bcarso]

I do a lot of reality-checking when running fourier when the numbers get low. One handy thing is to double the input signal and see what happens to the growth of the distortion components. In proportion to fundamental, if 2nd doesn't double and third get four times more then usually something is wrong with the numericals. Not always of course---if it's in the vicinity of a deadzone problem or "kink", like crossover distortion, this won't hold. But for typical ~smooth nonlinearities amenable to power series expansions it should hold most of the time.

IM distortion is also illuminating---use two generators and do the numerology to avoid coincident IM products, and a fine enough mesh in fourier to see all the stuff.

And yes, device matching is perfect (unless you go in and make it not so), and thermals are ignored without a whole lot of extra work. Also, how accurately is capacitance modulation modeled?

Regarding VAS distortion, you might want to check out a 1988 JAES paper by Hawksford someone pointed me to recently, Reduction of Transistor Slope Impedance Dependent Distortion in Large-Signal Amplifiers, vol. 36 no. 4. Good paper, although he is apparently unaware of much earlier work of Baxandall.

 

[Samuel Groner]

Brokaw gives a nice treatment of this in Williams' "Analog Circuit Design" book.

I just checked my copy and didn't find the specific implementation I mentioned (didn't read the entire text though)--can you give me the page number? Note that I'm not referring to the standard three-transistor Wilson mirror.

You might want to check out a 1988 JAES paper by Hawksford.

www.essex.ac.uk/dces/research/audio_lab/malcolmspubdocs/J10%20Enhanced%20cascode.pdf

Samuel

 

[Samuel Groner]

During some personal communications with Scott Wurcer he pointed me to a thread where he posted some schematics from early hybride amplifiers. Some of them actually implement some sort of JFET second stage buffer which inspired me to further investigate this possibility (particularly as it occured to me that this might enhance the common mode input range--more on this later).

I compared the following two implementations: JFET_VAS.gif

Note that I used a N channel JFET in place of PNP Q105. By using a matched JFET as active source load (Q206) it is easy to derive consistent bias (in the voltage domain, independent of temperature and supply voltage) and zero Vgs. The later property gives potentially higher positive input common mode range as the current mirror output can be operated at a higher voltage.

Some observations from SPICE simulations:
* Once the collector voltages for Q101/Q201 are matched (by adjusting R106/R205) the open-loop gain of both configurations is identical up to high frequencies (see JFET_VAS_gain.gif; red standard, blue JFET).
* The open-loop gain is identical if the basic current mirror is replaced with a Wilson type.
* The JFET implementation needs a feed-forward capacitor (C203) for good local Miller loop stability.
* The JFET implementation results in slightly worse phase margin.
* The JFET implementation shows higher THD above 1 kHz. The difference is modest though (just a couple of dBs) and would surely need verification in real world.

And some personal conclusions:
* For the tested configuration open-loop gain is not limited by current mirror output impedance or second stage input impedance. It is presumably limited by Early effect in Q106/Q207.
* The JFET implementation appears to be disadvantageous due to higher complexity, reduced phase margin and inability to cancel base current errors of the basic current mirror.
* The JFET implementation might be advantageous as it can potentially increase the positive CM input range by one Vbe.
* The gross distortion difference of the two implementations which was previously found and discussed in this thread is probably indeed a result of saturating the current mirror as already suggested above.

Samuel

 

[Samuel Groner]

A quick addition: if one wants to make use of the increased common mode headroom the JFET choice is critical. It needs low pinch-off voltage to work properly. With a (perhaps selected) J201 and a typical input stage one might realise a common mode input range up to half a volt below the positive supply. Pretty decent I'd say. Any other parts suggestions?

Samuel

 

[PRR]

> Any other parts suggestions?

An N-type enhancement MOSFET could have Gate slammed to or above V+ and still do a job.

 

[Samuel Groner]

But the bias is not easily made consistent and you run into output headroom troubles.

Samuel