Short answer:
> How do I choose the right bias level for Q14/Q15, i.e. the value of V4?
If the voltage across the FETs is too low, they quit working.
If the voltage is high, your Gate leakage increases.
If you apply a fixed voltage above the FETs, and have large input voltage swings, the fixed voltage across the FETs slams into the supply rail, limiting input swing.
> B: Assuming A is solved, what would be a suitable implementation of V4? Resistive voltage divider between supply rails? Something more advanced?
First: if there is any swing, you want to reference to the bottom of the FETs, not to ground as you show it. (And if there is no swing, why cascode?)
So tie your V4 battery to the FETs Sources.
Ooops, that puts the base resistance of the cascode BJTs in parallel with the long-tail. And you went to great lengths to build a high-Z long-tail. In fact that would be OK here.
But you probably don't want a floating battery. You want to derive a floating voltage from the rails, reference to the FET Sources, but not compromising long-tail impedance. Many ways to skin cats. One idea is a PNP emitter follower, Base to the FET Sources, a Zener running up from its Emitter and feeding the cascode BJT Bases, and a resistor from there to the supply rail to flow enough current to keep the Zener zenering and the bases well-fed. Or for AC use, the follower and a resistor divider with cap bypass to keep the FET voltages constant.
That still forces a compromise between ample voltage across the FETs and ample input voltage swing. You could of course just spec your rails much higher than your input swing. But if that is the only justification for high rail voltages, your accountant will hate you.
You can squeeze a little more by making V4 a function of Source-Rail voltage. Use the Zener to keep a constant FET voltage for input voltages from full-negative to half-positive. Bypass the Zener with a resistor, proportion so as your input swing above 10V, the FET voltage will sag from 5V towards zero. At some point like 2V, they will quit working, but they can be scaled to stay "working" with modestly degraded performance much closer to the rail than a fix-bias plan.
I'm not sure why you are cascoding (except, of course, the Quest For Understanding). Are you in trouble with Gate Leakage? Is your node inpedance potentially much higher than the FET Drain impedance? It may be at DC, but possibly not at AC, even 20Hz, because your compensation scheme will typically load this node.
You should also be aware that, while textbook JFET curves look like a Pentode, with very high "plate resistance", this is true for classical Long Channel JFETs. Short Channel JFETs have higher Gm and better Gm/C ratios, but much softer "plate curves". Don't complicate the project when a different FET might do the same thing. (No, I do not recognize the FET part number you used.)
