Comparison of JFETs for mic applications

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Voyager10

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Updated: see post #33 for more measurements
Good morning all!

I thought I'd share with you some measurements I've been making of various different JFETs, for use in impedance converter / amplifier applications in condenser mics. Specifically, how do the JFETs compare in the very widely-copied "FET amplifier + emitter follower" transformer-based design. RecordingHacks attributes this to the ADK A-51 originally (see http://recordinghacks.com/microphones/ADK/S-51) and it can be found in the MXL 2001 and V67 (https://groupdiy.com/threads/mxl.84887/), sE 2000 (https://groupdiy.com/threads/se-electronics.70694/) and relatives, Groove Tubes GT-55 (https://groupdiy.com/threads/groove-tubes.45261/) and many, many others.

I used the following circuit:

FET test preamp.png


The core of the circuit is the FET itself, Q1, drain resistor R4 and source resistor R3 (which set the AC gain), and variable bias resistor R2+VR1, which set the DC operating point. Almost all the clones use R4=20K. R3 is usually in the range 2K2-4K7, I'm using 2K2 for the maximum gain, as this will emphasise differences between the FETs.

There's an input socket J1, and the board allows the input coupling capacitor C_IN and the FET itself to be easily changed. For simplicity, the circuit was powered from a bench PSU and I omitted the output transformer - the output goes directly to an audio interface (and/or scope) for measurement.

Here it is in its box:

Mic test box.jpg

The FETs I had available were:
  • 2N3189
  • 2SK117-BL
  • 2SK118-GR
  • 2SK170-BL
  • 2SK208-GR
  • 2SK30A-GR
  • BF244B
  • J112

Next post: basic DC/AC measurements
 
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Basic measurements​


Each FET was put on the tester and the trimmer VR1 adjusted for 0.5mA drain current (measured as 10V across R4). This is at the upper end of the typical range and gives the highest transconductance and therefore gain. (The power supply was adjusted to ~20.9V so the filtered supply rail is at 20.0V). The gate-source voltage (across C1) was then measured which lets the bias resistor (R2+VR1) be calculated.

The AC gain of the circuit at 1KHz was then measured (the simplest thing at the time being to feed a variable voltage from a digital signal generator until I had exactly 1.00V pk-pk on a scope connected to the output). This was done first with a 1nF capacitor for C_IN, then a 68pF one.

I also measured the Idss current for each device (using the bench supply set to 7.5V and a DMM).

Here are the results:
DeviceIdss (mA) @ Vds=7.5VVgs @ Id=0.5mAR_biasGain (Cin=1nF)Gain (Cin=68pF)
2N381910.4-2.695.4K6.325.10
2SK117-BL7.25-0.372744R7.205.05
2SK118-GR3.8-1.422.8K6.254.78
2SK170-BL11.7-0.541.1K7.103.95
2SK208-GR3.51-1.252.5K6.334.70
2SK30A-GR3.69-1.462.9K5.954.90
BF244B9.9-2.605.2K6.305.30
J11237.2-2.625.2K7.005.10
 

Noise measurements​


For these I connected the test box to an audio interface (Focusrite Scarlett) running REW for analysis. The test procedure is:
  • First, apply 10mV RMS to the input jack J1. (The interface gain was set to give about -6dBFS at this point, but the exact setting is not critical - I didn't change it between measurements).
    • The signal came from an iPhone SE's headphone output and a signal generator app (because it avoided any ground-loop problems and I had already got a calibration table for output level vs headphone volume).
  • Using REW's RTA screen, use the 'Calibrate Level' button and enter 10mV. The RTA display can then be switched to show levels directly in dBV (as seen at the input of the test box).
  • Remove signal generator, put a shorting plug on the input, and screw the lid on the box. (Some mains hum is still visible, sorry).
  • Take & save a snapshot in REW.
This was done for each FET at C_IN = 1nF input capacitance and C_IN = 68pF.

1nF input capacitance​

Here is an overlay plot of all the devices, with 1/3-octave smoothing applied.

All devices, 1nF.png


68pF input capacitance​

All devices, 68pF.png

That's the raw data - not necessarily what you might expect! I'll post some thoughts later.

(I should add that these were all done in a single session, so the only changes for all the measurements were the input capacitor and the FETs themselves).
 
Some additional data:

A-weighted noise​

Here's the A-weighted voltage noise as reported by REW

DeviceCin=1nF (dBV-A)Cin=68pF (dBV-A)
2N3819-119.8-104.9
2SK117-118.7-103.8
2SK118-119.7-104.8
2SK170-117.8-104.5
2SK208-119.8-104.9
2SK30A-119.5-104.8
BF244B-120.0-104.7
J112-120.3-104.6

Provenance of devices​

These included 'everything I had on the shelf' so quite a varied history:
  • 2N3819: bought in 1990's, probably from Maplin or Farnell
  • 2SK117: eBay, Chinese seller
  • 2SK118: eBay, UK seller
  • 2SK170: bought > 5 years ago, small UK supplier, can't remember
  • 2SK208: Farnell
  • 2SK30A: eBay, Chinese seller
  • BF244B: again 1990's, Maplin or Farnell
  • J112: Farnell

Test setup noise​

Here's what the noise floor looks like with the FET replaced by a link from drain to source, which will include the effect of the resistors and Q2 as well as any preamp noise, alongside a typical 1nF plot from a FET:
No FET.png
 
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Awesome. It usually takes some time for me to wrap my head around these tests. Why 68M for gate resistor, and what's R8 there for?
 
68M is what I had handy, but it doesn't affect much. In the "68pF noise" tests, the FET gate has 68pF in parallel with 68M to ground, which has a -3dB point at about 35Hz. So, if the FET has any appreciable input noise current I'll be under-reporting it below 35Hz, compared to a setup with a 1G gate bias resistor. FETs have tiny noise current and the A-weighting curve basically ignores anything < 100Hz so I didn't worry (and I'm not averaging for long enough to get reliable LF noise readings anyway).

R8 was purely there to avoid nasty bangs through the headphones when plugging and unplugging the input jack..
 
Yes, I thought it was way out-of-spec at the time, but I've just re-measured and it's still huge. A couple of others from the same batch also measure 35-40mA.

Not necessarily a problem for this circuit - Idss is the current when the gate and source are at the same voltage, but in the circuit the gate is biased a long way negative which reduces the drain current.
 

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68M is what I had handy, but it doesn't affect much. In the "68pF noise" tests, the FET gate has 68pF in parallel with 68M to ground, which has a -3dB point at about 35Hz. So, if the FET has any appreciable input noise current I'll be under-reporting it below 35Hz, compared to a setup with a 1G gate bias resistor. FETs have tiny noise current and the A-weighting curve basically ignores anything < 100Hz so I didn't worry (and I'm not averaging for long enough to get reliable LF noise readings anyway).

R8 was purely there to avoid nasty bangs through the headphones when plugging and unplugging the input jack..
Thanks!
 
The 68pF graphs are the ones that count.

post 2 shows how the high input capacitance lowers the gain being a part of the feedback network at the JFET.

Think about JFET semiconductor C vs tube vacuum C
68pF distortion curves would add a lot to this work that you did
The JFET BJT circuits often use a PNP output

Compare what you built to the Brauner circuits that have been posted about

You might want to try a 33k or 47k at the JFET drain for low IDSS JFETs

IIRC 112s are often used as switches
 
Nice work so far. I wonder what kind of information did you want to elaborate?
My first point is that almost all JFETs you used show the same noise pattern. After looking upon the circuit you used it is clear that NOT the JFETs are noisy but other circuit elements.
R1 produces a current noise density of around 15 fAs^-0,5. In conjunction with 68pF that leads to a noise voltage density of 35 nVs^-0,5 at 1 kHz, at least 10 times more than the typical JFET noise (both voltage and current).
At higher frequencies (f.e. 20 kHz) the current noise density of R3 (2,2 k) dominates. It is equivalent to a noise voltage of 6 nVs^-0,5 and therefore 2 times higher than the JFET noise.
Sorry, but for the elaboration of JFET noise the circuit architecture is unusable...

Cheers MicUlli
 
Okay, a little bit unfair, i recommend the following changes:
1. connect - of C1 to GND
2. use 4G instead of 68M for R1
3. change R4 to 2,2K
4. use 9V block battery instead of 20V external supply
 
Sorry, but for the elaboration of JFET noise the circuit architecture is unusable...

I entirely agree, but that was not my intention!

The question posed in the OP was: given the circuit architecture (because it's used by many microphones) what difference do different JFETs make? Can you make a quieter microphone just by choosing a 'better' JFET, and keeping the same circuit? We are vigorously agreeing the answer is no, you can't.
 
What I think the 68pF noise plots are showing is that the JFET noise is insignificant compared to the Johnson noise associated with that capacitance (https://en.wikipedia.org/wiki/Johnson–Nyquist_noise has details), which will also render other circuit improvements redundant.

The next steps, for this circuit at least, are to look at distortion figures for the different devices, which might give some justification for choosing one over another.
 
I agree, the FET is not the bottleneck.
If you're aiming for linearity and low distortion, you need a different circuit.
like in the AKG C4000B. Drain gate capacity varies with voltage
Therefore this has to be kept constant.

In the AKG C4000 the FET works as source follower.

AKG uses a source follower with constant current sink,
as well the drain-gate voltage is kept constant.
source follower if used see Art of Electronics(Horowitz) Page 160.
 

THD Measurements​

Here are some slightly rushed measurements of THD for the first few FETs.

These were all done with the circuit shown above, and each FET was trimmed to 0.5mA bias as before.

The input source was 100mV RMS @ 1KHz, again generated from an iPhone + signal generator app.

For each FET measurements were made with Cin = 1nF and 68pF. (The 1nF figure reflects the basic nonlinearity, the 68pF figure will include any effects from the input capacitance or Miller capacitance varying with Vds, etc., and is more representative of performance of this circuit in a real mic).

The basic THD numbers reported by REW are as follows:

DeviceCin = 1nFCin = 68pF
2SK1180.11%0.058%
2SK1700.039%0.17%
J1120.25%0.34%


(For reference, REW reports the source signal as 0.00073% THD when input to the audio interface directly).
 

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  • 2SK170, 68pF.png
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  • 2SK118, 68pF.png
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  • 2SK118, 1nF.png
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Here's the full table for all the FETs

DeviceCin = 1nFCin = 68pF
2N38190.10%0.13%
2SK1170.061%0.14%
2SK1180.11%0.058%
2SK1700.039%0.17%
2SK2080.11%0.078%
2SK30A0.085%0.022%
BF244B0.038%0.071%
J1120.25%0.34%

(To be clear, these were done with a constant input voltage. For devices which show a lower THD at 68pF than at 1nF this is likely because the gain, and the output level, is lower).
 

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  • 2N3819, 1nF.png
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  • 2SK30A, 1nF.png
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  • 2SK117, 1nF.png
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  • 2SK208, 68pF.png
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  • BF244B, 1nF.png
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I entirely agree, but that was not my intention!
But still, you want this experiment to be relevant for condenser mics.
The 68Meg resistor is utterly inadequate, as MicUlli mentioned.
The problem is not the noise current of the FET, the problem is the KTC noise.
The spectrum of the Johnson-Nyquist noise produced by the resistor is low-pass filtered by the capsule's capacitance. Designers use the highest value compatible with good operation of the circuit, because it shifts the noise spectrum towards VLF, and accordingly decreases the noise density at audible frequencies.
Remember the actual perceived noise is the result of convolution of the noise spectrum and the audition process, which ignores frequencies below and above a certain range.
That's why, in order to be significant, noise measurements must always be band-limited, if not weighted.
 
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