Connecting CMOS logic gates in parallel

[audiox]

I am repairing an old measuring instrument. It has a complex discrete circuit that buffers 5 MHz square wave with low output impedance. The buffer is broken and there is no documentation available (it is not a factory made device and the designer lives in rest-home).

I replaced the whole buffer board with four 74AC540 gates in parallel. Each gate provides up to 24mA output current according to the datasheet. It works surprisingly well. Perfect square wave output dispite the low impedance load. It actually works so well that I came suspicious...

Are there any disadvantages in connecting the gates in parallel? I understand that if timing is not perfect, quite large currents can flow between the outputs. But I am using adjacent gates in the same chip, tied together with very short traces.

In have seen designs with a small series resistance in all outputs, but in this case it would increase output impedance too much.

74AC540 datasheet:
http://www.ti.com/lit/gpn/cd74ac540

 

[Svart]

I don't think there will be major problems at only 5mhz.  You could also use a FET gate driver which will offer low impedance drive ability without worrying about shoot through of the CMOS outputs.

 

[PRR]

Does it run HOT?

If not, I would not worry. CMOS (even this new stuff) is not as violent as TTL.

 

[jdbakker]

Are there any disadvantages in connecting the gates in parallel? I understand that if timing is not perfect, quite large currents can flow between the outputs.

You'll get small glitches at signal transitions due to tpd-mismatches. Probably not too harmful to the driver itself, but if this is a clock with ps-level jitter you're buffering you may want to look into other schemes. Apply enough decoupling so the junk doesn't end up in your power rails.

AC-logic is much faster than you need to buffer a 5MHz clock, unless you really need ns-level transition times (but it's doubtful the discrete driver you're replacing is that fast). If it were me I'd take a 74HC245, wire all eight I/Os on one side together and add a 4.7-10Ohm series resistor to each output before bussing them together (or get a pre-bussed resistor array).

If all this doesn't work, consider a video driver/buffer. Several modern fast op-amps fit the bill.

JD 'ADSL' B.
[best piece of advice I've ever received is to use parts that are fast/wideband enough to do the job, but no faster. Of course, that rule gets broken when it's Saturday afternoon and the demo is scheduled for Monday morning, in which case it devolves into 'find the square peg that best fits this round hole, and apply enough duct tape']

 

[audiox]

Jdbakker, thank you for great explanation - again.

Paralleling CMOS gates directly (without any resistors) is surprisingly common practice. It is used in almost all wordclock output stages that I have seen and in many AES outputs too. Even manufacturers like Studer and NTP do it regularly.

I guess the glitch problem is not that bad in practice? Saving two SMD resistors (0.001 euros) doesn't sound something that Studer engineers would do if it ruins the overall performance.

 

[jdbakker]

Paralleling CMOS gates directly (without any resistors) is surprisingly common practice. It is used in almost all wordclock output stages that I have seen and in many AES outputs too.

Both are very different animals.

Depending on logic family, package, number of gates and supply conditions simply paralleling multiple buffer/drivers adds somewhere between a few ps and several tens of ps of jitter. WC has much larger problems than that, and no designer in their right mind (and on more than a bargain basement budget) uses WC in without a narrowband PLL. Similarly, on typical cable runs AES can have a few ns of data-dependent jitter, so there too any ps-level driver jitter will be literally lost in the noise.

A low jitter clock inside a sampling or measurement system is a completely different story, and if the clock is properly done it's easy for a distribution amplifier such as the one you're describing to have a significant impact on performance.

JDB.
[then again, we know nothing about your device other than that it's a 'measuring instrument', and the cleanness of that 5MHz clock may not make any difference at all]

 

[audiox]

then again, we know nothing about your device other than that it's a 'measuring instrument', and the cleanness of that 5MHz clock may not make any difference at all

The instrument is a humidity measurement system that a friend of mine uses at his work. Jitter is definitely not a problem in this case. My intrest on the subject is more or less academic: I don't need that information for anything at the moment but it is always nice to learn somethig new.

My original concern was about reliability, but it is probably impossible to kill the chip by paralleling gates?

The 74AC series seems superior compared with 74HC. It provides output current 4-5 times higher and transition times in both directions are equal (that is what datasheet says). Still most of the manufacturers use 74HC for their AES and wordclock outputs. There is no difference in price. Is it more risky to parallel AC gates than HC? There must be some reason not to use "better" alternative. (Sorry but I don't have any practical experience of the 74AC series. I got the idea for my buffer from AES output of an AD converter. It used AC, so I did too.)

 

[JohnRoberts]

For reliability you can probably tell what you need to know by feeling the chip for temperature rise. If it runs cool it probably is...

JR

 

[jdbakker]

My original concern was about reliability, but it is probably impossible to kill the chip by paralleling gates?

Few things are truly impossible. This one is unlikely.

Does it run HOT?

If not, I would not worry. CMOS (even this new stuff) is not as violent as TTL.

For reliability you can probably tell what you need to know by feeling the chip for temperature rise. If it runs cool it probably is...

+1.

The 74AC series seems superior compared with 74HC. It provides output current 4-5 times higher and transition times in both directions are equal (that is what datasheet says). [...] There must be some reason not to use "better" alternative.

Like I said:

best piece of advice I've ever received is to use parts that are fast/wideband enough to do the job, but no faster.

AC logic is known to be temperamental when not properly bypassed. Even when properly bypassed, its faster transitions will make EMI and reflections much more of a headache.

JD 'better is in the eye of the beholder' B.

 

[audiox]

If it runs cool it probably is...

It is on the safe side: warm maybe but definitely not hot.

AC logic is known to be temperamental when not properly bypassed.

Uniform ground plane on one side of the board, all signal traces on the other side. 100n ceramic (HMD not SMD) multilayer directly from the VCC pin to ground plane. I guess that is good enough?

Even when properly bypassed, its faster transitions will make EMI and reflections much more of a headache.

I tried to find typical output transition times for 74HC and 74AC from the datasheets but no succes so far. It depends on load capacitance but there must be some "rule of thumb" values for typical applications.