Discrete Buffer Design

[bcarso]

Thomas, the LED is used because it has a relatively low impedance, for example compared to the equivalent resistor with the same voltage drop and current, and because it has a good match the the temperature coefficient of a Si Q base-emitter junction.

Because of that low Z, changing the current to the LED doesn't change the voltage that much, and therefore doesn't change the current out of the transistors that much. Jung was looking for a way to make the current constant and relatively independent of supply voltage. A PTC thermistor might help a bit, depending on its temperature coefficient at that operating point, but it's not clear how without detailed data on the thermistor. Also, if it changes too much the LED starts to get higher impedance and the current source may not work as well.

The suggestion to let the current sources have a negative tempco by using two or more diodes in series in place of the LEDs is maybe a bit more likely to be successful. This is after the Rs at the emitters of the driver transistors are adjusted upward to turn on the output stage properly, since that's when having only 2Vbe of tempco probably isn't enough to prevent thermal runaway.

You could also consider putting diodes in series with each driver transistor emitter, to provide two more Vbe's and their associated tempcos. BTW, PRR has just guessed at the roughly four Vbe's I believe---there's no guarantee there . This is a complex output stage. I did some sims myself but the program I use takes temperature into account with extreme reluctance.

 

[PRR]

> the LED drive current will drop, lowering the forward voltage and subsequently lowering the bias current.

Why would we do that?

We want a constant bias current in the transistors.

The bias current in the input stage IS the current source (or resistor) current. So we make that stable, input stage current is stable.

The Diamond Buffer topology is self-balanced for thermal drift. Looking at the top half, the equation is Vbe(PNP)-Vbe(NPN). Assuming Vbe/temperature matches between PNP and NPN, the output stage current is a multiple of the input stage current, which we already proved is fixed by the current sources.

We don't have to assume perfect PNP/NPN drift-match: the full 4-transistor topology has an equal number everywhere so the power supply current in both stages is set by the current sources (or resistors).

There is some difference between PNP and NPN. But in practice the thermal drift is small compared to the fact that "complementary pairs" have about 20mV more Vbe in PNP than in NPN. The Diamond Buffer always has about 20mV input-output offset. Over temperature it may be 15mV to 25mV, but we have to accommodate the basic 20mV offset which makes thermal offset drift a small matter.

Or to put it another way: Q1 Q2 are the thermal compensation diodes for Q3 Q4, and give gain as a side-benefit. This is one of the few simple self-compensated thermal designs possible. Enjoy, don't get clever.

I keep saying "current sources (or resistors)". For small signals it works just as well with resistors instead of current sources. All the bias stability remains (assuming rail voltages are stable). The problem with resistors is that the large-signal output impedance is R/Beta, which in practical cases either limits your output swing in low-Z loads or eats a lot of idle current.

As for adapting that Bryston design: I suspect that's like using a Ferrari or a Mack truck as a golf cart. Power amps have very special problems we don't face in line-amps, and special problems getting noticed in the over-crowded market.

 

[peranders]

I think we can make the conclusion that my, Glassman's (over at head-fi) or Jung's circuit is't particulary sensitive under normal working conditions. My pcb for instance uses the groundplane as temperature equalizer.

 

[barefoot]

[quote author="PRR"]..... As for adapting that Bryston design: I suspect that's like using a Ferrari or a Mack truck as a golf cart. Power amps have very special problems we don't face in line-amps, and special problems getting noticed in the over-crowded market.[/quote]
I don't want to discuss the final application here, but suffice it to say that I need a buffer that can drive a fairly challenging load efficiently, with minimal distortion, and near rail to rail output swings. So, I am thinking of this as sort of a mini Class AB power amplifier. And this is what lead me to consider the Bryston topography in the first place.

The biasing idea is really just a side thought because I know temperature stability is always a concern in power amplifiers.
The forward voltage of a typical red LED appears to increase by approximately 10mV per mA in the 10mA forward current range. (Vishay TLC.58 page 4) . The PTC thermistors have tempcos of about +3500 ppm, which translates to a +0.35% increase in resistance for every degree Celsius. Using a such a thermistor to drive the LEDs would yield an effective forward voltage temperature coefficient of around -0.2mV per degree Celsius. So, I'm pretty sure this would actually work at temperature stabilization.

You say this will adversely affect the performance of the input stage by introducing a less stable current source. My thinking was that it would create a quasi stable current source that reacts to relatively slow temperature drifts, but is stable with respect to audio signals. No?

Thanks!

 

[bcarso]

If you are willing to do some serious calculation as evidenced above, more power to you. Just know what you are getting into---that output stage design is not for the faint of heart.

Some PTC devices have a very nonlinear characteristic and will have gigantic swings at critical temperatures, useful for some protection apps for example. They are not very precise either. Some are more genteel and you may have those in mind, like the ones developed to compensate log amps. These are not typically easy to obtain otoh. The good old silicon Vbe/diode tempcos are relatively close to one another (although see Pease's curves in the back of Troubleshooting Analog Circuits for graphs of many different possibilities). The fortuitous tempco match of GaAsP "standard red" LEDs to Vbe junctions is useful because of the excess voltage available across the emitter resistor in these current sources, but note that the tempco match is best at a given pair of bias currents, and that you want the LED to be a reasonably low impedance for the circuit to work well. Hence, don't reduce its current too much, and make sure it is always much more than base current.

If your temp. compensation is primarily for changes in ambient temp., that's easier to manage. Just have lots of fin area on your power devices, oriented to facilitate convection, and decent ventilation. But you will have to determine through modeling, experiment, hand calculation, or the combination, just what the real tempco situation is. If you are simultaneous fighting h.f. oscillatory behavior in your output stage this will complicate matters. Again, note well Bryston's remarks on multiple sensors. In their case the chip temp swings with signal are way too large to follow the only-ambient-comp strategy. Maybe in your app they will be as well. When you get to needing the compensation for signal-induced changes, you run into the problem of very long thermal time constants, even with the sensor devices right at the device package, and associated problems of time-lagged over- and under-compensation, transient crossover distortion, etc.

As far as the effect of the 3500ppm/degree C thermistor on the output of the partial Jung stage, I calculate -4.75uA/degree C change in the LED bias resistor current of nominally 1.36mA. Taking your 10mV/mA LED characteristic as given, that results in about a -47.5uV/degree C change in voltage across the 220 ohm current source R's, or a current change due to that of -216nA/degree C. This has an effect on each driver Q emitter + 10 ohm R voltage of about -216nA times 16 ohms (10 ohms + r sub e at about 4.3mA) per degree C. This is only 3.4uV/degree C (if I haven't screwed up somewhere), or about twice that for both driver outputs. This is a small effect compared to the exisiting delta Vbe of order 4.4mV/degree C.

We don't know what you need yet for the output stage, but it is safe to say you need more than this.

Brad

 

[PRR]

> can drive a fairly challenging load...

What is "challenging"? Headphones? 600Ω? Fully loaded freight train?

> ....efficiently

And that opens a can of worms too. In audio, normal signals, the average power is far lower than peak power. So idle power tends to dominate system design, particularly if the word "battery" is on your plate.

The Jung will approach 40% efficient, at full power. But it has the same power drain at zero signal. I suppose that's why you don't want it. This of course will be the situation for any true class-A amp.

A good class-AB amp hits 60% 70% efficiency at full load (measured at the rails; supply losses may reduce overall efficiency to 50%). And it can idle at low power.

How low? In theory, zero, of course. But that gives crossover distortion, which may not matter much for a motor-driver or a speech communications system, but really bites music. NFB can only do a little to fight crossover distortion: NFB works by using excess gain, and through crossover gain is low.

So your output impedance, at idle, before global NFB, should be less than your load impedance. If you have a lot of voltage gain, 600Ω could be driven from 0.1mA biased devices. But the voltage gain stage eats current too. If you don't have excess voltage gain, then the bias current has to be up around 5mA for fairly low crossover distortion, hence something like the Jung.

What is your power goal? You could probably design a 600Ω driver that idled at 0.25mA. But if worked to +18dBm it will suck 5mA. What does that do to your power system?

Efficient "power" amps are not complicated, though good sound can be subtle. Read Doug Self. Especially the common flaws: "bad" amps are often not due to unsophisticated topology, but simple mistakes like where you connect various grounds, returns, and feedback. You can be sloppy in a low-efficiency design, but the honking half-waves in a class AB design make a lot of trouble. Then scale-up the resistances from 8Ω to your desired load. That may get silly for 600%#937;: you might scale-up by 10 or 20 and omit one stage of emitter follower.

 

[PRR]

> the existing delta Vbe of order 4.4mV/degree C.

Isn't it zero mV/C +/-~0.2mV/C?

In the Jung, the PNPs and NPNs Vbes cancel. The drift is much less than 2mV.

The thermal runaway problem in speaker amps is a function of heatsink area. There is a size where the devices will drift without running away. That size is costly compared to bias-diodes which give order of magnitude compensation, but in a 100mW output with TO-93 devices the required heatsinking may be just the bare devices, no extra sinking.

Another issue: the Jung is normally biased/run Class A. If it is stable at idle, it will not runaway under load as a Class AB output might. (It might have the opposite problem: it runs cooler when loaded and working hard.)

 

[bcarso]

PRR quotes me "> the existing delta Vbe of order 4.4mV/degree C. "

I meant the half-Jung piece, as proposed to be grafted to the bryston piece by barefoot, not the full diamond buffer. Yes the temp comp of the diamond is as you say very good. I've used various versions of that complete stage many times and never had a problem.

 

[bcarso]

On further pondering I may still not be making myself clear here.

What I was trying to express is that, from the top of the upper 10 ohm of the half-Jung to the bottom of the other 10 ohm of the half-Jung, the magnitude of that voltage will change at about -4.4mV/degree C.

Actually, at that current density the change is probably closer to -4.0mV/degree C.

 

[peranders]

The Jung buffer is pretty stable so I don't really understand what you are refering to. Any schematic?

 

[bcarso]

We're talking about driving and temp compensating the bryston stage with the half-Jung buffer, as proposed by barefoot. There is no issue with the tempco of the full Jung buffer per se. It's small, and the initial offset voltage is low, and negligible when enclosed in an overall feedback loop.

The voltage differential of the half-Jung stage, and its tempco, applied to the input bases of the bryston stage, should be such as to (1) turn on the bryston stage adequately, and (2) have an ambient temperature coefficient so as to keep the bryston stage happy, that is, neither current-starved nor current-bloated. Barefoot wants a relatively efficient design that swings nearly to the rails.

I'm all in favor of the full Jung stage per se and mindful of its limitations. We're just trying to explore the issues around the original post's design. It does have the appeal of a bit of voltage gain so that the driving source need not swing to the rails. It has many disadvantages, among them difficulty of easy analysis ;-).

 

[barefoot]

I altered the circuit a bit and I'd like to see what you all think.

Trying to keep things as easy as possible, I made the following simplifying assumptions:

1. All diode drops and VBE's are exactly 0.6V
2. All hfe's are high so IC=IE

Does my biasing analysis look right?

 

[bcarso]

The biasing analysis looks correct.

 

[bcarso]

In sim it looks a lot better now. The output stage is running a little richer than your estimate at about 4.5mA per MJE device, and that's before they warm up. With much smaller lead caps across the 1k R's (100pF is way high---6.8pF is about right) and driving 600 ohms, the response is peaking-free and -3dB at 21MHz. If inside a larger loop you will have phase issues to deal with well before that frequency. If the layout is not quite tight you will have lead inductance effects that may vex.

Distortion is low and the structure is level-dependent a bit. Respectable when driven from a voltage source in front of the 100 ohm at a predicted 560 ppm for 40V p-p out, 1kHz. Inside a feedback loop things will be different.

I used BAS16 diodes because my simulator 1N4148 model is bogus, but that shouldn't make a huge difference.

 

[barefoot]

Thanks bcarso!

Now that we're starting to narrow in on a design, I guess I should label the components so we can identify things a little more easily.

How do things look if the load is more like 50 ohms? I would imagine C2 and C3 need to be increased to around 22pF?

Also, does your simulator model the complimentary devices differently? I'm interested in knowing if there are any significant performance enhancements from matching betas and/or VBEs between the NPN and PNP devices?

 

[bcarso]

Ummm...my sim just takes the models they can find from contributing manufacturers. In fact I'm using supposed equivalents for the MJE parts because the simulator doesn't have them as such, just the ECG equivs.

There are no true PNP/NPN complements in all parameters---it's just the nature of the beasts. Holes and electrons have way different mobilities in Si. Bipolars are capable of being made closer as complements than FETs though. When Bryston says they match them they mean in some specific parameters---maybe beta at some current(s).

The 6.8pF's, C2 and C3, are still ~optimum at heavy loading. With a 50 ohm load the gain drops due to the roughly 5 ohm output R, and distortion rises precipitously, to about 0.4% for 3.6V p-p out. But it must be mostly crossover distortion (indeed it is dominated by third), because for 36V p-p out it's down to less than 0.1%.

Running richer bias would help, but then you want efficiency. Inside a larger loop it probably won't much matter.

 

[barefoot]

[quote author="bcarso"]With a 50 ohm load the gain drops due to the roughly 5 ohm output R, and distortion rises precipitously, to about 0.4% for 3.6V p-p out. But it must be mostly crossover distortion (indeed it is dominated by third), because for 36V p-p out it's down to less than 0.1%.
[/quote]

That doesn't seem too horrible considering it will be in a feedback loop. Appears to be on a similar par with distortion specs I recall seeing for the Jung Super Buffer driving a low impedance load and running in full Class A.

 

[barefoot]

While we're at it, it might be cool to see how this circuit would perform driving a speaker size load.

What if?

Load = 6 Ohms

R3, R4 = 220 Ohm
R7, R8, R9,R10, R11, R12 = 200 Ohm
R13, R14, R15, R16 = 100 Ohm
R17, R18, R19, R20 = 1 Ohm
Q9, Q12 = D45H11
Q10, Q11 = D44H11

Man, I need to get a discrete circuit simulator! :grin:

 

[bcarso]

"Man, I need to get a discrete circuit simulator! "

Good grief yes man. Int*l ought to give you one---after all sooner or later we're going to be analog again, albeit in ways we may not see as yet.

 

[barefoot]

I downloaded the demo version of Micro-Cap this morning and spent a few hours setting up my buffer and getting accustomed to the software.

Fantastic! I should have been using this ages ago!

Model import is disabled, so you have to type in all the parameter for new components. And you can't save any new components to the library. The way I found around this was to create all my new component models within an empty circuit file. I named it Model-Template.cir. Whenever I want to create a new circuit I just open this template and save it under a new file name. It contains all my models, so I'm good to go.

The 50 component limit is the real drag. I ran into that pretty fast. But I guess that's the price you pay for saving $4000 off the full version! :grin:

I'll post latter with some optimized versions of the buffer (the Barefoot Buffer? :wink: )