wow ok I'm going to have to read that a few more times but I think the part where it said the 2 signals do not have to be symmetric but must have the same impedance. Thank you so much for all your help!
wow ok I'm going to have to read that a few more times but I think the part where it said the 2 signals do not have to be symmetric but must have the same impedance. Thank you so much for all your help!
when I added in the series resistor and capacitor in parallel with the drain resistor, the signal that gets outputted from the drain gets an LPF as desired but the signal from the source does not which creates what I believe is an unbalanced signal...
I was wondering for a while now but forget to ask, output pair gets different impedance output from FET(source out has lower impedance than drain), does this reflect in anyway to the pair output, if you get what i mean. @Khron and others are welcome to chime in.Two different concepts, signal symmetry (is pin 2 signal the same but opposite polarity as pin 3 signal), and impedance balance (is the impedance from pin 2 to the chassis the same as pin 3 to the chassis).
For noise rejection with a differential input the impedance balance is what needs to be maintained. The impedance at each pin is determined by the PNP emitter-follower circuits, so the balance will be maintained even when the signal is not symmetrical.
What will change with a frequency-dependent difference in only one leg is the slope of the combined output.
For my derivation of that see this earlier post.
Why not?XLR connectors were not galvanically connected to the screen
As per AES convention, the shells should indeed be connected to pin 1 (screen).
OK, thanks; then I've been misinformed about that. Anyway, all of my XLR cables are AES54-1 compliant and do not have pin 1 connected to the shell.
Jan
Enter your email address to join: