Implementing FET Switch

[JohnRoberts]

It looks like it will work.

I have already stated my preference for an alternate approach that reduces errors due to Rds on.

I don't recall the breakdown voltage of J111 but you can tolerate higher rails by putting diode clamps to ground at device drains. These will be out of the picture when devices are conducting and when they are deselected it will prevent positive input signal swings from exceeding breakdown voltage wrt VEE.

EDIT: you need to use clamp diodes connected in both polarities to prevent pumping DC back into the blocking capacitor.

There are always multiple ways to skin any cat... enjoy.

JR

 

[Samuel Groner]

Thanks--it is not clear to me however where (and for what reason) I need to add clamping diodes. Can you elaborate? By blocking capacitor you mean C116-C118?

Samuel

 

[JohnRoberts]

Sorry, I though I said... At the drains of the JFET switches.

If the JFET is switched off and high impedance the drain will swing the full AC input signal, while at the same time it's gate is held to a voltage more negative than the most negative swing to prevent conduction. The delta between this very negative gate drive and positive signal swing may exceed breakdown voltage for some devices.

OK I "broke" down and found a J111 data sheet... The breakdown voltage looks adequate at 35V considering a 10v worst case pinch off and only +/- 12V rails. If the rails were +/- 15V it could be an issue.

The diode clamps in addition to reducing gate breakdown demands during positive swings, prevents conduction issues during negative signal peaks with less negative gate drive voltages.

Worst case design tolerance without clamps looks like gate drive needs to be 10V more negative than -12V or -22v. This -22V relative to +12V peaks is 34V total which gives you 1V safety margin... no sweat.

In practice and for one off DIY, the pinch off voltage will be closer to 3V than the 10V worst case, and opamps don't swing hard to rails so +/- peak swing will be less than 12V which helps in both considerations.

A similar benefit to diode clamps could also be gained from a resistor to ground at the drains instead of the diode clamps but this would increase noise gain of the circuitry when selected.

After doing the math you can probably get by with the circuit as drawn (I don't recall what you're using for VEE). In production (if for some reason I couldn't clamp or use alternate approach) I'd be tempted to cheat a few volts on the VEE (less than -22V) to provide more than 1V of breakdown safety margin. Conducting on occasional very negative peaks will be the less objectionable fault mode.

This will be more of a concern with lower breakdown voltage parts and/or hotter rails. YMMV

JR

 

[JohnRoberts]

Blocking cap C114

JR

 

[Samuel Groner]

Thanks, makes much more sense now--I mainly missed the point about the drain seeing the full voltage swing when switched off.

As VEE is just -12 V and the maximum expected negative input voltage is -10.5 V I might better be using the 2SK170 as suggested by Brad (VGS_off > -1.5 V). That way I'd be able to skip the clamp diodes (unless I'm still missing a point) which I don't really like as they inject rectified currents into ground which can hardly be a good thing, even if the effect might be benign given good grounding.

Samuel

 

[Samuel Groner]

Thanks, I've seen that. Initially I discarded that idea as it's more complex and I don't really need low distortion and good offness, but I'll think about it again. Perhaps I can skip the shunt switches to avoid the inverters so it's just two resistors and two caps more than the current approach (and in turn two transistors less).

Samuel

 

[JohnRoberts]

If worried about the linearity of ground currents the resistor to ground instead of diode clamps buys you several volts more working range but with different considerations (noise floor).

If you are not listening to this circuit path, or using it to detect distortion, linearity is not paramount. I would argue the 'Switch inside the loop" is more precision but the fact that you are trimming the result means your main concern is gain stability after it is trimmed not precision before.

I am not familiar with temperature coefficients for (JFET) Rds on but temperature does seem to make a difference in the active region between on and pinch off. Piling more speculation on top of that, 0V Vgs is not hard on. You can actually get slightly lower Rds on by forward biasing the gate diode. This is generally avoided because the gate current would then contaminate the channel current. My point is there is still some modulation left in channel conductance beyond 0V. I don't know how much control device designers have over this (temp co) but 0Vgs would be a good operating point to optimize for.

Perhaps Brad or someone more versed in the device physics will chime in with some actual facts instead of my speculation. It is clear embedding the switches inside the feedback loop will reduce any sensitivity to temperature, it is also pretty unlikely that this is a big problem. Even a significant temperature coefficient will be minimal in the context of this circuit. Even less considering the temperature range bench equipment is exposed to.

Your circuit is OK as drawn, this is just the typical over analysis I routinely enjoy performing on (other people's) designs.

JR

 

[bcarso]

[quote author="JohnRoberts"]
Perhaps Brad or someone more versed in the device physics will chime in with some actual facts instead of my speculation.
JR[/quote]

**Ding**

IIRC the tempco of resistance of bulk silicon (due to the negative tempco of the majortiy carrier mobility) is about (EDIT) 0.6-0.8%/degree K around 300K. EDIT: (that's positive; the "contact potential" of the gate-channel diode has a negative tempco, which allows a given FET to have a first-order zero-tempco operating point, typically with a gate-source voltage about 0.6V more in the "on" direction than the magnitude of the pinchoff voltage----see Cobbold's book and many others)

It's intriguing to consider the slightly-forward-biased condition.

 

[bcarso]

PS: The zero-temco issue would emphatically NOT be something to consider using FETs as analog switches. It just occurred to me that someone jumping into what was a switch thread might get the wrong idea if they didn't read all the posts.