low jitter clocks
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jdbakker
Well-known member
The common techniques include:
- use a resonator with high Q
- in an oscillator with low noise
- fed by a low noise low impedance supply
- limited by a low noise limiter/comparator/clamping amplifier
- phase locked to a reference with low phase noise
As usual, context is important. What are you trying to achieve ? Building a standalone master oscillator for, say, an ADC or a CD transport ? Locking an oscillator to a studio word clock / house sync ? Do tell ;-)
- use a resonator with high Q
- in an oscillator with low noise
- fed by a low noise low impedance supply
- limited by a low noise limiter/comparator/clamping amplifier
- phase locked to a reference with low phase noise
As usual, context is important. What are you trying to achieve ? Building a standalone master oscillator for, say, an ADC or a CD transport ? Locking an oscillator to a studio word clock / house sync ? Do tell ;-)
jdbakker
Well-known member
OK, that narrows it down a bit.
At the risk of being too obvious, you can't get a 44k1 clock from a 24.576MHz signal. The LCM of 44k1 and 48k is 7.056MHz; assuming you want sample clocks at 64*Fs your master oscillator needs to run at 451.584 MHz to be evenly divisible. So either you need separate crystals (or oscillators), or one VCO with a wider tuning range which is then locked by a Phase Locked Loop. The latter technique has more phase noise.
Do you want to build or buy ? If you want to DIY, I've heard positive reports about the Kwak Clock by Elso Kwak (just Google for it, or Google for "crystal phase noise" if you feel like spending a few weeks wading through links and research papers ;-)). If you want to buy, in my experience there tends to be a positive correlation between XO tolerance/drift and phase noise, ie the lower the frequency tolerance, the lower the phase noise, with most regular XOs being noisier than most VCXOs, and TCXOs being even quieter. Again, this is no fundamental oscillator property, just observed behaviour.
[edit: typo corrected]
G
Guest
Guest
[quote author="jdbakker"]
At the risk of being too obvious, you can't get a 44k1 clock from a 24.576MHz signal. [/quote]
Why not?classical PLLs are rather obsolette,
Do jou know work of Ulrich Rohde ???
http://www.holmea.demon.co.uk/FracN/Synth.htm
And for original theme - low jitter oscillator -oscillator must be very
near the sampler (ADC) because of jitter generated by spurious signals
induced to clock feeder.
xvlk
At the risk of being too obvious, you can't get a 44k1 clock from a 24.576MHz signal. [/quote]
Why not?classical PLLs are rather obsolette,
Do jou know work of Ulrich Rohde ???
http://www.holmea.demon.co.uk/FracN/Synth.htm
And for original theme - low jitter oscillator -oscillator must be very
near the sampler (ADC) because of jitter generated by spurious signals
induced to clock feeder.
xvlk
jdbakker
Well-known member
Thanks for the interesting link (I happened to be looking for a differential limiter), but I don't see how it has a bearing on this thread. The original poster said he wanted to divide down (which is one of the few sane ways to get a low noise derivative clock), and I pointed out that 24.576MHz can't be divided into 44k1. PLLs, classical or not, weren't mentioned anywhere.
If, like the original poster, you're looking for a low noise master clock, I would strongly recommend staying away from any kind of PLL. The base system noise of most phase comparators is much worse than what you can achieve with a good high-Q crystal tank. Besides, what are you going to use as a reference clock ? If you happen to have a low-noise ref clock design, why not use it for the sampling clock you were interested in in the first place ?
JDB
[who realises that, in a studio, one might need a PLL to lock to word clock. Just keep in mind that, with a good free-running Xtal oscillator, that will likely raise your clock jitter]
If, like the original poster, you're looking for a low noise master clock, I would strongly recommend staying away from any kind of PLL. The base system noise of most phase comparators is much worse than what you can achieve with a good high-Q crystal tank. Besides, what are you going to use as a reference clock ? If you happen to have a low-noise ref clock design, why not use it for the sampling clock you were interested in in the first place ?
JDB
[who realises that, in a studio, one might need a PLL to lock to word clock. Just keep in mind that, with a good free-running Xtal oscillator, that will likely raise your clock jitter]
featherpillow
Well-known member
Yes. Well, you mean building it to have low jitter in the first place.
Just build a low-jitter clock to house in your...what unit are you building it for? A good internal clock is a better place to start than a good external clock. Make that a secondary project. A divide by 1024 or 512 or 256 is what you'll need to divide down the master clock rate.
A good place to start unless you need higher master clock rate. I think it will do 24.576 at the most, right? That leaves you hanging if you need 49.152 or 45.158.
In my experiences, I couldn't hear anything different between 100ppm's and under, and I know others who have reported similar things. TCXO is going to be a tough one to find in the right frequencies. I question its necessity unless you're working with SMPTE.
Otherwise you'll get a funky distortion in your audio--I suspect it's from phase errors between the clocks in question.
