wow --- i'm beaming with pride... :green:
Mac*ie TT24 I presume ?But last week I had access to a product based on this chip.
Mac*ie TT24 I presume ?[/quote]But last week I had access to a product based on this chip.
Yes that is right.i think THAT's how JLM did it
#include <msp430x20x3.h>
void main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P1DIR |= 0x01; // Set P1.0 to output direction
SD16CTL = SD16REFON + SD16SSEL_1; // 1.2V ref, SMCLK
SD16INCTL0 = SD16INCH_1; // A1+/-
SD16CCTL0 = SD16UNI + SD16IE; // 256OSR, unipolar, interrupt enable
SD16AE = SD16AE2; // P1.1 A1+, A1- = VSS
SD16CCTL0 |= SD16SC; // Set bit to start conversion
_BIS_SR(LPM0_bits + GIE);
}
#pragma vector = SD16_VECTOR
__interrupt void SD16ISR(void)
{
if (SD16MEM0 < 0x7FFF) // SD16MEM0 > 0.3V?, clears IFG
P1OUT &= ~0x01;
else
P1OUT |= 0x01;
}
#include <msp430x20x3.h>
void main(void)
{
volatile unsigned int i;
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
P1OUT = 0x10; // P1.4 set, else reset
P1REN |= 0x10; // P1.4 pullup
P1DIR = 0x01; // P1.0 output, else input
USICTL0 |= USIPE7 + USIPE6 + USIPE5 + USIMST + USIOE; // Port, SPI master
USICTL1 |= USIIE; // Counter interrupt, flag remains set
USICKCTL = USIDIV_4 + USISSEL_2; // /16 SMCLK
USICTL0 &= ~USISWRST; // USI released for operation
USISRL = P1IN; // init-load data
P1DIR |= 0x04; // Reset Slave
P1DIR &= ~0x04;
for (i = 0xFFF; i > 0; i--); // Time for slave to ready
USICNT = 8; // init-load counter
_BIS_SR(LPM0_bits + GIE); // Enter LPM0 w/ interrupt
}
// USI interrupt service routine
#pragma vector=USI_VECTOR
__interrupt void universal_serial_interface(void)
{
if (0x10 & USISRL)
P1OUT |= 0x01;
else
P1OUT &= ~0x01;
USISRL = P1IN;
USICNT = 8; // re-load counter
}
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