Simulation anomaly

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ruffrecords

Well-known member
Joined
Nov 10, 2006
Messages
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Location
Norfolk - UK
Attached is a pic of the LTspic sim I use for looking at the open loop gain of my twin line amp design - the one that has recently been acting as a great amplifier for unwanted signals over 1MHz. I have been using this to see if there is anything inherent in the design that might be responsible for this.

So, V1 represents the input via a mic transformer looking like a voltage source with a 15K source resistance. The 150V connected to the 47K resistor replaces the dc voltage that would be supplied by the SRPP output stage if the 47K was not disconnected from the output so we see the open loop response.

With the default values, looking at the grid of U2 the mid band gain is about 14dB and the response us 3dB down at about 34KHz and continues steadily downwards thereafter. However, if you reduce V1 sourece resistance to 150 ohms, to simulate int being driven by the output of another stage like this, a peculiar thing happens. Again looking at U2 grid the response is 3dB down at about 34KHz but it does not drop steadily thereafter. Instead it reaches a minimum and then starts to rise again in the several MHz region.

If you disconnect the grid of U2 and look across the 1Meg, the response drops as you would expect. In the model used for U2 all I can see is a 11.7pF capacitor between the grid and the cathode of U2. Adding 12pF across the 1Meg (with the grid disconnected) does not produce the rising response of the original circuit (presumably because the 12pF is to ground rather than the cathode of U2).

I am puzzled by what is happening here. I don't know if it is a real effect that may have some bearing on the operation of the circuit or if it is just a simulation oddity.

I can post theL Tspice files if anyone want them.

Cheers

Ian
 

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I've given up on simulations some time ago, it seems that the results that are genuinely interesting sonically won't show up anyway. At least with today's component models.

That aside, I would add a grid stopper (1K?) resistor to the lower-part ECC88 - it's a simple way to calm hysterics in the 88´s

Jakob E.
 
ruffrecords said:
The 150V connected to the 47K resistor replaces the dc voltage that would be supplied by the SRPP output stage if the 47K was not disconnected from the output so we see the open loop response.
This may be the reason for the strange sim. The subject has been discussed at length on the LTspice group. I suggest you submit your circuit there and someone will orient you towards one of the preferred methods, that involves breaking the loop with a B-source, so the loads are undisturbed. I'm away from home now so I can't give you the references, but Helmut there is always friendly and reactive.
 
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