Very Odd Comparator INPUT phenomenon- hoping for an explanation!

[jBam]

Hi All...

A strange thing has popped out while SPICE modelling.  I hope someone can explain this - I wouldn't normally ask about random SPICE moments, except this weird thing is producing almost exactly the signal I want... but it's popped out in the weirdest place!

I'll try to explain briefly and accurately:

1. I have a comparator which is picking when one signal is higher than another (nothing weird there).
2. This is supposed to then send a logic signal to a couple of inverted CMOS switches to open and close and swap between signals... Cool - I've made that work before...
3. NOW - when I add a resistor in between a buffer and the Comp's input, and read a voltage from between this resistor and the input, I see that the signals are combining at the INPUT side... in a really interesting way too...
4. If I increase one resistor, it changes the amount and way that the signals combine at the input side too.  In fact - it's almost doing the exact switching I was after, but a lot smoother than I expected my actual design to do it - and I can't help but want to use this signal now haha...

Can someone please explain if this is unusual or a typical outcome - i.e. what's going on here?!... It's naturally only there when I pop the resistor(s) in there at the inputs (as otherwise the buffers smash out whatever the comparators need which overrides this subtle combining of signals feeding back from the comparator.

If interested, please have a look at the attachment...

The two comparator inputs PRE resistors (out of buffers) are in Red and Blue.
The green line is in between the resistor and the comparator input.

When you look at the green line carefully, you notice that it has a non linear relationship with the others until it ultimately matches back into the blue line...  It's basically a super smooth combination of the two, with very little phase delay.  Notice also that at high peaks where red is above blue, the green line tracks relatively close, but then further along between 410.4s to 411s it's tracking quite far off, before sliding back into to match the blue line once the signals are no longer close enough to interact...

This is basically the exact control signal I'm after in this new design; it's just at the wrong end of the circuit haha...!

Please let me know if you understand this!

 

[abbey road d enfer]

1. I have a comparator which is picking when one signal is higher than another (nothing weird there).
2. This is supposed to then send a logic signal to a couple of inverted CMOS switches to open and close and swap between signals... Cool - I've made that work before...
3. NOW - when I add a resistor in between a buffer and the Comp's input, and read a voltage from between this resistor and the input, I see that the signals are combining at the INPUT side... in a really interesting way too...

It would be much easier if you attached a diagram, with the impedance of the source

 

[jBam]

It would be much easier if you attached a diagram, with the impedance of the source

Yes - fair call Abbey...  I was a bit carried away by the outcome!

I'm away from the studio at the moment...  Source impedance in that image was an equal 10k in front of each input of the comp.  I tried it with 1k and 100k in front of one end only (10k on the other input) with notable variation in the way the signals combined.

My guess is that it's something to do with very low impedance inputs on the comp where these additional resistors promote some signal leakage / mixing on the input terminal side that is still influenced by the comp output swing (hence why signals are more influenced by one or the other when there's a larger variation between the two...? But that's just a guess.

Wasn't sure if this is common though?  Certainly results in something I want (which is kind of annoying under the circumstances of it being accidental).

I'll post up a mini schem tomorrow with part No's...

 

[jBam]

Hi again - refer attached for a basic schem.  It's got a few additional buffer stages in there that I'm not sure are necessary; but I've labelled the important element, and where the weird mixed signal was measured. 

Note also that this version goes to two comparators; but the effect is still valid with only one connected (with two connected, the effect is basically twice as strong though, as the input feedback (for want of the correct term!) is happening twice.

The comparator I've used may seem like an odd choice, but all testing (after hours and hours of optioneering) suggest this works best in the application.  Regardless, it's an interesting phenomenon that I'd like to understand!

Here's the LT1721 datasheet for anyone REALLY interested(?):

http://cds.linear.com/docs/en/datasheet/17201fc.pdf

Page 21 (simplified schematic) suggests it's input impedance is at least  150ohms.... but the rest of that is a nightmare for me to understand (and I don't expect anyone here to really go through that in detail!)...

Note also - this is the only comparator I've found where I get such a pronounced effect... BUT:  with an alternative LT1716 in there, and cranked up input resistors (up to 1Meg+) I start to see the phenomenon sneak back in there too... So it certainly seems to be something that is not unique to the 1721.

 

[abbey road d enfer]

Hi again - refer attached for a basic schem.  It's got a few additional buffer stages in there that I'm not sure are necessary; but I've labelled the important element, and where the weird mixed signal was measured. 

Are you sure the voltage you apply to the inputs of the comparator are within the usable range? What is the rail voltage going to the comparator? It should not exceed 7V total.
Now I don't understand what you expect this circuit to do... As I see it, if you apply a sinewave to Signal 1 and nothing to Signal 2, the output will be a single-wave rectified sine.
And if you apply sinewaves to both, the output will be an erratic sum of fractions of sines...
If you want to create some kind of ducking effect, with the output being the loudest of the inputs, you have to add envelope detectors.

 

[jBam]

Are you sure the voltage you apply to the inputs of the comparator are within the usable range? What is the rail voltage going to the comparator? It should not exceed 7V total.

Yeah - everything is well within limits - rails are 5V+/-...

*** And as I type, it all falls into place***

Wait... LT1721 is single supply.  I've set it up as dual... tsk tsk...

**WAIT** And then I've just now ran a sim with single supply and it's all still happening; so we're back on...!

Now that that's out of the way --> So yes, it's (now) all within usable range.

---------

As for what it's intended to do?  Well as per usual, it's an odd(ish) idea...  The intent was to swap between + DC control signals (which ever was higher) in a dynamics sidechain idea I've been messing with.  Specifically a brickwall limiter design where the signal soft clips above the threshold on the attack, and then decays once this soft clipped signal lowers below a more standard filtered decay signal.

I've got the soft clipper part sorted and working - very adjustable / precise.  Then I've quickly hacked into a comparator / CMOS rectifier design I've developed in the past (hence the rail voltage screw up here as I rushed it) and found this weird effect with the LT1721....

Like I said, this odd signal is annoyingly doing exactly what I want; better than I expected... it's a nice smooth hysteresis effect between each signal - with out any jumps I'd expect at the end of the intended circuit due to gates opening and closing; AND without the phase delay associated with filtering out and clicks/bumps from gates which would screw up how the soft clipping works in my circuit... problem is --> the signal's appearing in the wrong spot; and I don't feel comfortable about considering it usable unless I can understand why it's happening!!...

Not sure if this idea is useful or not yet though haha...

That said, I do greatly appreciate your responses though Abbey.

 

[abbey road d enfer]

The intent was to swap between + DC control signals (which ever was higher) in a dynamics sidechain

What is the range of these control voltages? Is it really necessary to have two comparators?

 

[jBam]

What is the range of these control voltages? Is it really necessary to have two comparators?

Short answer is no!... It's a bit of a hangover from the rectifier design which adopted differential outs into CMOS switches (on high). An alt to even that would be one switch with on high; another with off high and a single output comp.

I hacked two of these 172x into this circuit to work within the same basic design, and instantly was impressed by the (modelled) accuracy and speed of the output (although that had the dual supply cock up; the single supply still works very nicely too). Then I noticed the thing that prompted this thread; searched the net for an explanation with no luck, and popped on over to here to discuss!

 

[abbey road d enfer]

Short answer is no!... It's a bit of a hangover from the rectifier design which adopted differential outs into CMOS switches (on high). An alt to even that would be one switch with on high; another with off high and a single output comp.

I hacked two of these 172x into this circuit to work within the same basic design, and instantly was impressed by the (modelled) accuracy and speed of the output (although that had the dual supply cock up; the single supply still works very nicely too). Then I noticed the thing that prompted this thread; searched the net for an explanation with no luck, and popped on over to here to discuss!

You haven't answered the most important What's the range of incoming signals?

 

[jBam]

You haven't answered the most important What's the range of incoming signals?

Well within working limits... 0-1V typically peaking around 800mV.

Like I mentioned though, I've also tricked a another comparator into this (modelled) behaviour too - but had to crank the input resistor up a lot (over a meg if I recall correctly). It was dual supply, same signals and also well within working limits.

It's basically like: if I crank up an input impedance significantly great than than the inbuilt input impedance, the whole chip flows back into the pre-circuit.  Makes sense to me within my limited knowledge... But it's a strange effect and interesting (and will likely make sense somehow rather than being a modelling glitch)...