While we're on the subject of differentials...

[featherpillow]

I did a preliminary search for this, but couldn't find anything. If this question has already been answered in another thread, just point me to it...

Typically, we operate a differential from a bipolar supply, but the circuit shown uses a single-sided supply (I guess it's similar to PRR's different differential in that respect).

When putting this circuit together, Horowitz and Hill tell me that R3 should be chosen to give about 100uA to the collector of Q2, and that no collector resistor is needed for Q1 because no output is taken from there. R1 provides a reference voltage for the transistor bases, correct? And R2 sets input impedance...

They tell me that gain is calculated as R3/(2 x R6+R4).

Third, they tell me that CMRR is roughly R6/(R4+R5).

Fourth, R6 is chosen to give emitter current of about 200uA, but maybe that doesn't matter with a single sided supply...?

Given these, I'm trying to figure out a way to put this circuit together with relatively high CMRR and unity gain. If I omit R4 and R5 entirely, differential input impedance drops, and the differential gain goes up (if I understand this part of the analysis correctly--I'm not sure that I do). If I increase their size, CMRR goes down. Do you see my conundrum?

If I substitute a current source for R6, I can substantially improve CMRR, of course. But how can I do that with a single sided supply?

 

[bcarso]

"If I substitute a current source for R6, I can substantially improve CMRR, of course. But how can I do that with a single sided supply?"

Just a lower tap on a voltage divider supplying the base of a bipolar current source, or a two-diode bias, or an LED, or replace the whole thing with a JFET CCS, or a current reg diode, etc.

You will want a stiffish voltage divider and then individual larger Rs to each base of the pair of course, or individual voltage dividers (not as good---why?)---as drawn the schematic shows how CMR would be tested. And you will want a.c. coupling unless the source happens to sit at the voltage divider potential. Pick the input coupling C's with an eye to cap mismatch screwing up CMR at anywhere approaching the cutoff frequency, i.e., make them larger than necessary at first glance.

Doing unity gain with this stage will entail a fairly restricted output voltage swing.

 

[featherpillow]

Just a lower tap on a voltage divider supplying the base of a bipolar current source, or a two-diode bias, or an LED, or replace the whole thing with a JFET CCS, or a current reg diode, etc.

Oh, of course! I can't believe I didn't think of that! The goal is to keep the emitters of the differential less positive than the collectors and bases while biassing them from the existing positive voltage source, right?

You will want a stiffish voltage divider and then individual larger Rs to each base of the pair

So R1 isn't going to cut it by itself? Is there a rule of thumb or formula that's helpful here?

or individual voltage dividers (not as good---why?)

Hmm...would it be because of the potential for DC voltage differences to appear at the bases and emitters of the pair? Wouldn't this have a negative effect on the intended operation of the circuit?

And you will want a.c. coupling unless the source happens to sit at the voltage divider potential.

Right--AC coupling isn't shown in the schem, but I included it on the breadboard. I assume any difference in DC potential between the source and the circuit in question would have negative effects on operation, right?

Doing unity gain with this stage will entail a fairly restricted output voltage swing.

I hadn't thought of that. Why is this? I understand how a circuit can swing within close proximity of the rails using a bipolar supply, but I don't quite understand how it works using a single-sided supply and reference voltage.

 

[bcarso]

I need to know the application's conditions to further explain the restriction on signal swing---is it really a balanced source, or a situation where the major swing relative to common is on the n.i. input, and the other input just is rejecting a bit of common-mode noise?

In a circuit with substantial gain the differential signal swing is small compared to the output swing---hence the bases can sit fairly close to the negative rail, or in this case common. How low will be also constrained by what the current source needs to function properly. Look at the conditions in the circuit when the collector of the output device is swinging lowest, and keep in mind that the voltage on the base at that point can't be more than a few tenths of a volt more positive. If the drive is truly diffrential then the base is going positive while the collector is going negative. Then add to this condition whatever the common-mode signal you are trying to reject might be. Depending on what the signals are going to be this can be pretty restrictive. If you are only going to swing a couple of volts with a reasonable +vdc then no problem.

There are many circuit mods that add parts to enhance signal swing. One fairly simple one would be a common-base PNP turnaround stage which you can bias to have the collector sit roughly at 1/2 +vdc.

Realize as well that the output Z of this circuit is essentially the same as the collector load R, so it will get loaded down easily and the gain will be correspondingly less. If you know your destination's input Z the R can be adjusted upwards to compensate, but then this will restrict output swing further.

 

[featherpillow]

The idea is to use it as a balanced microphone input. The goal is to achieve a single-ended output, and unity gain, which would only involve a few millivolts of "wiggle" as Misters H and H put it.

If output Z is roughly the size of the collector load, would it be best to buffer the output of the differential before sending the signal into the next stage?

 

[bcarso]

[quote author="featherpillow"]The idea is to use it as a balanced microphone input. The goal is to achieve a single-ended output, and unity gain, which would only involve a few millivolts of "wiggle" as Misters H and H put it.

If output Z is roughly the size of the collector load, would it be best to buffer the output of the differential before sending the signal into the next stage?[/quote]

OK fine. You will achieve a more-or-less equal input Z w.r.t. common at each input at least. But realize you will be corrupting your signal with noise. Is the wiggle level differential and common-mode? Why wouldn't you want at least some low-noise gain, if it is a mic level signal?

As far as the output, yes, buffering with an e-follower would be prudent if you are not certain of your load, or have to drive a cable very far.

 

[featherpillow]

Is the wiggle level differential and common-mode? Why wouldn't you want at least some low-noise gain, if it is a mic level signal?

The wiggle is differential and common-mode, yes.

I was under the impression that this circuit has common-mode rejection, and that it's independent of differential gain.

I'm guessing that this is mistaken--rereading the H & H analysis, it seems as though the circuit has both differential and common mode gain, but the goal is to keep the CM gain extremely small while making the differential gain large.

If there's no differential gain, the stage becomes somewhat useless in terms of noise rejection, right?

 

[bcarso]

Unity diff gain is still gain in that sense. And equal input impedances will confer noise rejection from disturbances equally induced into a balanced line, depending on the common-mode rejection.

But a decent (balanced input) mic pre will do the same.

 

[PRR]

> R6 is chosen to give emitter current of about 200uA, but maybe that doesn't matter with a single sided supply...?

It does. Q1 and Q2 don't have to be run at equal current, but they have to be near-equal. If you don't aim for near-equality, then at some extreme of signal, supply, or temperature you wind up with one transistor cut-off, which radically changes things (not for the good).

> I was under the impression that this circuit has common-mode rejection, and that it's independent of differential gain.

No. This plan has a common-mode gain of "about one", and differential gain can be very high, so CMRR can be high.

You are adding the additional constraint that diff-gain is unity. Therefore CMRR is "about one".

Why is common-mode gain "about one"? For a moment, ignore R4 R5. Say you decide to bias R6 with 10 volts, take 10V drop across Q2, 10V drop across R3, near-equal current in Q1 and Q2. R3 is then half the resistance of R6. CM gain is then 0.5, "about one". In many amps, output swing is important while supply voltage is expensive; you are tempted to reduce the "waste" voltage on R6 so you can increase the available swing on R3, which leads to CM gain closer to unity. Using relatively large values for R4 R5 (to get your unity diff-gain) leads to similar increase of CM gain. To get substantial decrease of CM gain, you would go to very large drop on R6: 100V on R6 with 10V drop on R3 gives CM-gain about 0.05, so with diff-gain set to unity your CMRR is about 26dB. But over-100V supply may be awkward. 10V on R6 and 1V on R3 gives the same gains, but maximum output is less than a volt, which may be insufficient.

A current-source will reduce your CM gain and raise your CMRR, but you still have the unity-gain problem: when the base of Q2 goes high, its collector goes low, and pretty soon the collector runs into its base/emitter and Q2 stops working transistor-style. So the peak input and output swing at unity gain is less than half the supply voltage.

This plan makes sense when you need high diff-gain. It runs into trouble at low diff-gain.

Most diff-amps do.

Can you live with diff-gain of 2? And a chip? There is a sweet 2-opamp diff-amp with low noise. And if you were really going to take mike signals into BJTs biased at 100uA, you can probably do better noise figure with the quietest chips.

The truly elegant solution, for mike-like impedances and levels, is a transformer.

 

[featherpillow]

Thanks for taking the time to further explain, PRR.

I'm beginning to understand the problem associated with these constraints.
Continuing my work with the text, I've noticed that there is indeed a relationship between these two values. Differential gain in the circuit above is R3/2(R4+R5), whereas Common Mode gain is -R3/2(R6+R4). And as you've stated, PRR, when Gd is high, CMRR is high.

I've taken the time to redraw the schematic using bcarso's suggestions, and I set supply at 48vdc, as an homage to your differential, PRR :grin: :

I've set collector current at double what Horowitz and Hill initially recommended--about 200uA. Voltage at the bases of Q1 and Q2 are 1/2 of VDC, and the voltage at the base of Q3 is about .25 of VDC. bcarso recommended a stiff divider, hopefully these values are stiff enough. I calculated the value of R11 at .25 of R4. Differential gain is 10, but my guess is that it should be set higher if this gets used as a mic input stage. Common mode gain when using a current source becomes effectively 0 according to H&H. I added an output buffer as well.

Any comments or corrections?

 

[bcarso]

What I meant by a stiff divider is one common to the two bases, with individual R's from the divider to each base. That way you get the same potential, rather than depending on two sets of 1% Rs to bias each base.

That divider can be pulling a few mA and then 100k Rs to each base gives you relatively high input Z.

As drawn now you probably intended R2 to be 49.9k. But I would give the current source its own divider, or better a couple of series diodes for lower Z and some power supply rejection. Right now you are modulating the current source with one side of the signal.

Also Q4 needs a resistor from the emitter to ground, and the signal output taken from the emitter. The input coupling C's are on the wrong side of the 1.5k Rs.

I almost got my photobucket account to work the other day and then they had an outage, which I assumed was something I was doing wrong. Alas I have been under the gun lately and it looks like that will continue for a while. This is good because I need the money, but frustrating wrt the forum et al. Expect better communications when I get my graphics act together---this is truly a case of the picture being worth a boatload of pedantic blather.

 

[featherpillow]

What I meant by a stiff divider is one common to the two bases, with individual R's from the divider to each base. That way you get the same potential, rather than depending on two sets of 1% Rs to bias each base.

I think I know what you're talking about. I've redrawn the schematic. I see the reasoning behind using a single divider--we want to keep the DC potential on the two bases the same.

Right now you are modulating the current source with one side of the signal.

Now, that you've pointed that out, I can see the problem with setting up the CCS this way.

Also Q4 needs a resistor from the emitter to ground, and the signal output taken from the emitter.

Right now, I'm trying to figure out what the value of that resistor should be...

 

[bcarso]

Take the lower ends of R2 and R6 to the center of a voltage divider, some few-several volts above ground. For example 30k to 10k to ground, so the divider center tap is sitting at 10k/(30k + 10K) * 48V or about 12V.

Have your two diodes in series have their lower cathode go to ground. Run the top anode to the base of Q3. Put a 47k from +48 to that same junction. You have now developed about 1.3V at the base of Q3, and have about 0.65 at Q3 emitter. The current out of Q34's collector will be 0.65V/R11.

Reverse the polarity of the input coupling caps.

Samuel Groner's schematics for various of his op amps show this type of I source---also Tamas (tk@halmi).

Chimay ale is delicious---could almost substitute for wine OOOPs wrong thread. Happy 4th! :razz:

 

[featherpillow]

Okay, here's the latest incarnation:

 

[bcarso]

Now you're talking. Realize now that R3 needs to be about 2 * 6k or 12k for unity gain, if R13 is open, given little loading by the emitter follower. You can then tweak bias of the diff pair bases for optimal output swing, though with low level inputs there won't be a problem.

Or, you can let R3 get larger and get some gain, within the constraints of the output voltage swing running into the Q2 base voltage swing. Note that in these circuits the output d.c. level is linked to the gain---R13 can help you only if you want the voltage to be lower than contrained by the gain, unless you tie R13 to a voltage higher than +vdc.

For more gain independent of tail current you could put a PNP current mirror up top---mirror Q1's current and tie that mirrored output to the collector of Q2--- and load that junction of collectors with a voltage divider from +vdc to ground. The gain will be about twice the impedance at the voltage divider center tap divided by 12k, since you will have both collectors contributing to the output current signal.

 

[featherpillow]

Note that in these circuits the output d.c. level is linked to the gain---R13 can help you only if you want the voltage to be lower than contrained by the gain, unless you tie R13 to a voltage higher than +vdc.

I put R13 there as a divider (and forgot to set value). I was reading in H&H about emitter followers, and they say I should use a voltage divider so the base sits at 1/2Vcc. Is this applicable here or no? Now that I'm thinking about it, I'd say not--we don't want the collector of Q2 sitting at 1/2Vcc because of that divider, right? I'd have to capacitor-couple the emitter follower in order to avoid that...

 

[bcarso]

Yep---H&H are talking about an e-follower in isolation, and you are providing the given d.c. voltage for its base with the circuit already. And 1/2 V+ is not optimal because of the other voltage swings, although if those are small enough what's to worry.

This is a good exercise in constraints and tradeoffs.

 

[featherpillow]

This is a good exercise in constraints and tradeoffs

It's a great learning experience for me--thanks so much for your help! :sam: (that's not a Sam Adams, it's a Chimay)

 

[analag]

Just wanted to put this here
http://www.angelfire.com/ab3/mjramp/ampdes1.html

 

[featherpillow]

Hey analag--thanks for the link. That looks like the Douglas Self stuff I'm reading right now about input stages.