Philip_BlueFX
Active member
Hey, I am trying to figure out this whole section of the 1176. Playing with it on my breadboard while I follow the Gyraf DIY schematic.
The whole BC547 section (I call this the "AC Split" section) looks pretty straightforward to me. It creates two out-of-phase copies of the input signal (comin off the pre-amp out), attenuated heavily by the voltage divider. Closed Loop Gain looks to be about 10 with the 47k Resistor.
Now, I believe the Q-Bias pot is there to provide a constant negative voltage to the FET's gate when no signal is coming in so that it doesn't attenuate unless it needs to.
For a 2n5952 this point seems to be around -3V, where the FET presents maximum inner-resistance. However, rotating the 'RELEASE' pot I notice that this point is heavily affected.
From what I understand, the voltage at FET's gate needs to be consant and goin positive (-3 to 0 from what I observe) in order to compress. The 2.2M resistor causes voltage drop so I measure about -5V at the charging cap to get -3V at the Gate.
I am trying to understand if the Release pot is supposed to change this bias point. Maybe I oversimplified this concept in my head but it ain't so. Anyone care to elaborate?
On an earlier post someone mentioned (think that was Jacob) that the FD333 low-leakage diode is supposed to minimise this effect so I went with BJTs instead of the 1n4148s I first used since I can't find the FD333s anywhere nearly accesible.
The whole BC547 section (I call this the "AC Split" section) looks pretty straightforward to me. It creates two out-of-phase copies of the input signal (comin off the pre-amp out), attenuated heavily by the voltage divider. Closed Loop Gain looks to be about 10 with the 47k Resistor.
Now, I believe the Q-Bias pot is there to provide a constant negative voltage to the FET's gate when no signal is coming in so that it doesn't attenuate unless it needs to.
For a 2n5952 this point seems to be around -3V, where the FET presents maximum inner-resistance. However, rotating the 'RELEASE' pot I notice that this point is heavily affected.
From what I understand, the voltage at FET's gate needs to be consant and goin positive (-3 to 0 from what I observe) in order to compress. The 2.2M resistor causes voltage drop so I measure about -5V at the charging cap to get -3V at the Gate.
I am trying to understand if the Release pot is supposed to change this bias point. Maybe I oversimplified this concept in my head but it ain't so. Anyone care to elaborate?
On an earlier post someone mentioned (think that was Jacob) that the FD333 low-leakage diode is supposed to minimise this effect so I went with BJTs instead of the 1n4148s I first used since I can't find the FD333s anywhere nearly accesible.
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