YES@Bobby Baird wow, thank you for all that info! Very helpful indeed!
Okay, so to sum up, it would look like this, right?
Bypass - DPDT on-none-on
Threshold - DPDT on-off-on
Release - SPDT on-off-on
Pad - SPDT on-off-on
YesIC1 - THAT1246
YesC17-C20 - 0.1uF electrolytic caps
From THAT 1240 series datasheetOut of curiosity, you show a picture above that appears to show several ceramic caps connected between Input and Chassis ground. Would you mind elaborating on what that is? Is that also to do with the 1246, or unrelated?
To reduce risk of damage from ESD, and to
prevent RF from reaching the devices, THAT recommends
the circuit of Figure 4. C3 through C5 should
be located close to the point where the input signal
comes into the chassis, preferably directly on the
connector. The unusual circuit design is intended to
minimize the unbalancing impact of differences in
the values of C4 and C5 by forcing the capacitance
from each input to chassis ground to depend primarily
on the value of C3. The circuit shown is approximately
ten times less sensitive to mismatches
between C4 and C5 than the more conventional
approach, in which the junction of C4 and C5 is
grounded directly.