chilidawg
Well-known member
- Joined
- Nov 27, 2013
- Messages
- 184
Well, I hope this is correct...
Simulation for SMUX2 96KHz.
signal IN_VCO is from Texas Instruments TLC2932A PLL VCO output pin, 256fs.
signal OUT_WCLK_FB is this clock signal divided by 256, send to PLL input pin B.
1 period in time = 10416.640 ns = 96000Hz.
signal OUT_SCLK is IN_VCO
signal OUT_BCLK is 64fs
signal OUT_WCLK is fs
signals OUT_SDA0, OUT_SDA1, OUT_SDA2, OUT_SDA3 are four I2S serial 2:1 multiplexed 32 bit audio data (24 bit audio data + 8 bit padding)
signals OUT_M2 & OUT_M3 are Cirrus Logic CS4382A hardware standalone registers for setting the frequency rate (1x/2x/4x), which I will probably remove soon because in serial control port mode, it can accept 256fs system clock instead of 128fs at 4x frequency rate.
Simulation for SMUX2 96KHz.
signal IN_VCO is from Texas Instruments TLC2932A PLL VCO output pin, 256fs.
signal OUT_WCLK_FB is this clock signal divided by 256, send to PLL input pin B.
1 period in time = 10416.640 ns = 96000Hz.
signal OUT_SCLK is IN_VCO
signal OUT_BCLK is 64fs
signal OUT_WCLK is fs
signals OUT_SDA0, OUT_SDA1, OUT_SDA2, OUT_SDA3 are four I2S serial 2:1 multiplexed 32 bit audio data (24 bit audio data + 8 bit padding)
signals OUT_M2 & OUT_M3 are Cirrus Logic CS4382A hardware standalone registers for setting the frequency rate (1x/2x/4x), which I will probably remove soon because in serial control port mode, it can accept 256fs system clock instead of 128fs at 4x frequency rate.
