Not understanding. The output stage of an IA is usually an op amp (integrated or discrete) with the required (very) low output impedance.
Example would be useful to clarify
Balancing an unbalanced circuit
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Not understanding. The output stage of an IA is usually an op amp (integrated or discrete) with the required (very) low output impedance.
Example would be useful to clarify
k brown
Well-known member
Here's one I saw; Kev Ross SSM2017 schem:
Why not just connect the 2017 to the 2142? The 833 provides another 6dB of gain, but why not just raise the 2017 gain by 6dB? Is this just to increase the overload margin of the 2017?
Why not just connect the 2017 to the 2142? The 833 provides another 6dB of gain, but why not just raise the 2017 gain by 6dB? Is this just to increase the overload margin of the 2017?
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ruffrecords
Well-known member
I don't get it. With low Z sources bipolar inputs are usually quieter than FET.
I have a feeling you're looking for an explanation where there is not.
I don't think that the extra 6dB gain justifies that, neither the polarity inversion.
The most probable explanation is that the "designer" put the opamp there in prevision of needing much more gain, but realized it was not really necessary in practice.
The CMRR of these circuits is seriously impaired when driven by a non-zero impedance.
With a nominal 1k impedance, only 10 ohms limit CMRR at less than 60dB. 100 ohms=>40dB
I see what you mean. It does look like a gain staging / dynamic range thing from the designer ??? Unless there's also something I've forgotten re SSM2017 output ? (not that I think so). I'd also question why the 833 op amp. Unless that is simply indicative of an opamp gain stage. The schematic has few other minor issues ?
If you look at the circuits you'll see that any significant source impedance degraded performance. But I see Abbey has pretty much covered this
Yes. Misunderstanding I think. I think you have read "cf" as "of" ?
I was using "cf" as an abbreviation for "compare". I wouldn't usually but being as bit lazy as on holiday so mobile phone touch keyboard. So that didn't work out
. OTOH I can see Mount Vesuvius from the window. Against that it's too (expletive) hot 
But I digress.
Yes - in general - bipolar for low voltage noise and the usually higher current noise less important with decreasing source impedance. And vice versa (to risk "going Latin" again). Obvs I know you know this.
Thanks for the heads-up about the AES preprint 4126 (about hardware in Sony-Oxford console), published in Oct 1995. For the record, I applied for my application for InGenius (US Patent 5,568,561) in Apr 1993 and it was granted in Oct 1996. I'd be very curious if SSL had published anything about their common-mode bootstrap "in the mid-'80s." Nothing showed up in prior art searches in 1993.
But, in any case, the bootstrap circuit shown in Fig 14 of the AES preprint (attached) has significant differences that significantly limit its ability to raise common-mode input impedance. Note in Fig 14 that the source of the common-mode voltage is extracted by resistors CM1 and CM2 from the output of the differential stage (whose CM gain is unity), as it is in my circuit. But this circuit then, through a coupling capacitor, directly drives input bias resistors CM3 and CM4 - and more importantly, the unmarked ground-return resistor. This arrangement effectively forms a voltage divider for the CM voltage, consisting of the paralleled CM1/CM2 and the ground-return resistor. Since the multiplication of the values of CM3 and CM4 is proportional to 1/(1-Av (where Av is gain of the loop from diff-amp outputs to the junction of CM3 and CM4), this divider limits how close the loop gain can approach unity. My design inserts a unity-gain buffer between the junction of CM1/CM2 and the coupling capacitor, allowing loop gain to exceed 0.999. This truly makes the input CM impedance comparable to a transformer. I also note that the composite diff-amp (TR1, TR2, OP1, and OP2) uses inductors to degenerate HF gains of TR1 and TR2 to avoid the noise penalty of using a resistor for the same purpose - just as Deane Jensen did in his famous 990 audio op-amp module.
Also of note is Fig 12 from the same preprint (attached), where "TYPICAL IMPERFECT RECEIVER WITH UNEQUAL INPUT Z" is used to describe the garden-variety op-amp and 4 equal resistor "diff-amp." In the context of common-mode impedances, which are what's wholly responsible for the noise rejection in a balanced input stage, this statement is wrong! The input impedances of the two legs of this stage are different ONLY when driven one at a time. If driven together (which, by definition is what "common-mode" is), the impedances are equal. For years, this property of the simple diff-amp has been blamed for all its shortcomings - and, for almost 30 years, I've been trying to set the record straight. The problem with this, or any of its cousins, is that the values of the resistors can't be made high enough (tens of megohms) to achieve transformer-like CMRR without the terrible noise penalty of high-value resistors. It has nothing to do with its quirk about inputs being driven separately. I'm well aware that engineers do everything from messing up the resistor values to adding another op-amp (i.e. "super-bal") to "fix" this perceived problem. And I'll end with another myth: signal symmetry (equal but anti-phase) on the two lines has absolutely nothing to do with noise rejection!
ruffrecords
Well-known member
Maybe I am being thick. The 1646 is a line driver. Its input is unbalanced so how does driving that affect the CMRR of the balanced output?
Cheers
Ian
Matt Syson
Well-known member
Interesting discussion so far. As ever there are so many factors going on 'out there' be it the ability to have good numbers for 'specmanship' to quite subtle 'one liners' that get thrown in. the SSM2017 can and does oscillate if the capacitive load on it's output is too great with the spec sheet quoting 50pF as a maximum to ensure stability. Then there is the question whether having 'perfect' CMR that is reliably maintained from DC to Ghz could ever be achieved. Then the ability to withstand both ESD to a real world level, and accidental mains voltage application (240VRMS for anything considered 'international'). Mr Rupert Neve (RIP) was a fan of bootstrapping and he produced designs for mic and line level input stages, as well as a cross coupled line output stage.
I am a little frustrated that the IC implementations of cross coupled outputs have no readily available mechanism to define the offset polarity of the outputs meaning that bipolar output coupling capacitors are necessary. For usual interstage coupling it is relatively straightforward to 'design in' offset determination by using relatively high input biasing resistors with a bipolar op amp. The (mostly SSL scheme from the 1980's was to use a pair of electrolytics, back to back and pull the 'centre of the 2 caps to a power rail using a high value resistor. In the days (1970's) when capacitor bias current was a 'thing' the single rail circuitry used by Audix used 'double coupling (2 caps in series with centre taken to 'switching ground' to eliminate switch clicks as the 'leakage' (reformation current) of the first capacitor would leave a couple of millivolts of residual DC.
Then there could be the discussion about the use of servos to 'eliminate' offsets which doubles the op amp count making things hotter and more likely to drift.
I am a little frustrated that the IC implementations of cross coupled outputs have no readily available mechanism to define the offset polarity of the outputs meaning that bipolar output coupling capacitors are necessary. For usual interstage coupling it is relatively straightforward to 'design in' offset determination by using relatively high input biasing resistors with a bipolar op amp. The (mostly SSL scheme from the 1980's was to use a pair of electrolytics, back to back and pull the 'centre of the 2 caps to a power rail using a high value resistor. In the days (1970's) when capacitor bias current was a 'thing' the single rail circuitry used by Audix used 'double coupling (2 caps in series with centre taken to 'switching ground' to eliminate switch clicks as the 'leakage' (reformation current) of the first capacitor would leave a couple of millivolts of residual DC.
Then there could be the discussion about the use of servos to 'eliminate' offsets which doubles the op amp count making things hotter and more likely to drift.
Matt Syson
Well-known member
Morning Ian
A good question. I haven't looked but I think that the internal cross coupling resistances with one creating the inphase output and another the out of phase need to see a low source impedance as internally the design 'input' is a bit like a simple diff amp with same value input resistors so as noted previously the input impedances are different when viewed in isolation. Or I am completely wrong and it is just too early in the morning for me!
A good question. I haven't looked but I think that the internal cross coupling resistances with one creating the inphase output and another the out of phase need to see a low source impedance as internally the design 'input' is a bit like a simple diff amp with same value input resistors so as noted previously the input impedances are different when viewed in isolation. Or I am completely wrong and it is just too early in the morning for me!
Matt, you're absolutely right. Looking at the block dgm of the 1646, it shows that the + input receives negative FB from the + output, and the + input receives NFB from the - output. If a parasitic resistance is introduced in one of the inputs, balance is compromised.
It has always amazed me that many brilliant designers fell into this trap, when it is quite easy to debug, using basic opamp equations. No need for Spice or rocket science.
Matt Syson
Well-known member
The 'inverse parallel' protection diodes on some bipolar op amps can catch you out on some circuits as they can get 'zapped' by transients which then create 'noise' but the input transistors still function correctly. A useful observation in Walt Jungs book from 1983 eventually came in useful in 1998 as it had festered in the back of my head unused.
I've never seen that, but recall reading in the classic Motchenbacher and Fitchen "Low noise design" text (decades ago) that if low noise transistor base-emitter junctions are allowed to reverse bias and zener, they can become noisy. That's why the anti-zener diodes are commonly used (reverse emitter to base) in many low noise input stage designs.
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wrt simple 4 equal resistor differential stages, true a signal into the + input resistor bootstraps the opamp - input up to 1/2 the + resistor input V, but a signal into the - input alone sees the - input resistor to a virtual earth. Common mode signals by definition are coming into both inputs at the same time so the bootstrapping effect of negative feedback makes the CM impedance siimilar, differential mode (actual audio) signals can see different + and - input impedances. This is a subtle difference. I have used truckloads of simple differential stages inside SKUs driven from low impedances where impedance balance didn't matter. For claimed balanced (cough) inputs I prefer fully symmetrical input topology.
I can't opine about driving the 1646 because I never used one of the sundry canned I/O devices inside a design. I worked for a sharp pencil value engineered company and op amps were cheap. We even had 1/10% resistors in the system so effective balanced input and outputs were cut and paste from well proved designs for tens of cents. I don't doubt that Bills design is better on the test bench, but ours was adequate for our customer's typical applications.
I never used a canned input or output solution. I've told the story many times about the features I wanted the IC makers to include (in dedicated output drivers), and that they never did.
JR
Matt Syson
Well-known member
The problem with too much overthought is simply that and as nice as it might be to have superb CMR there are so many other factors going on that you can chase your tail endlessly for no actual benefit. If a 1646 (and whatever is attached to the other end) can manage excellent CMR, can it manage to stay 'interference free' up to a few hundred KHz without extremely careful board layout and any internal unit wiring/copper traces? Do you get 'matched' ferrite beads/feedthrough capacitors and where do you stop? The SSM2142 output driver can and would die if designers failed to fit protection diodes up/down to the rails to catch spikes from people shuffling on nylon carpets when patching audio jacks. Incorporating suitably robust diodes on the die ought to have been posible (1N4000 series was proposed as a workaround). Then you get 'fashion' and the 'fad' to fit Burr Brown parts because somebody on the internet says they 'sound' best.
Indeed. The very notion of CMRR pertains to a connection, including a source and a receiver.
It is based on the Wheatstone bridge, which contains four impedances, two in the source and two in the receiver. Qualifying CMRR of one or the other is tentative to produce quality index that just does not reflect the real world result. Not mentioning cables...
Coincidentally speaking about device pin protection, years ago I had a discussion with THAT engineer Gary Hebert about repurposing one of their balanced input/output chips into a precision synthesized current source by using a custom metallization layer to reconfigure how the precision resistors were connected. Since their basic silicon supported different common gain ratios, there were enough precision resistors available for my current source. A custom metallization layer is not cheap, but far cheaper than making a dedicated IC.
The stopper that killed my project request was that the synthesized current source needed one more input/output pin than their existing part. The THAT die had just enough I/O pin transient protection wells for the standard application. My extra I/O pin would have to be left unprotected, and that was considered unacceptable to them.
They understand that customers blame them when the chips fail no matter the fault.
JR
