Explain this circuit to me - Output Protection?

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barefoot

Well-known member
Joined
Jun 4, 2004
Messages
93
Location
Portland, OR
Can someone explain the highlighted section of this circuit to me? It appears to be some sort of soft-start, anti-thump or output-short-protection arrangement, but I can't really figure it out.


3BST-Schematic-highlight.gif


Thanks,
Thomas
 
That's a good guess. As the plus rail comes up, it pulls in the relay, and thus, un-shorts those two emitters. That's as far as my brain will go.

When I see stuff like that, I rip it out of the circuit, since I don't know what it does, and eliminating one more potential failure source in a power amp makes my heart soar like an eagle. Knowledge replaces fear, no knowledge rips out excess baggage.
 
Yeah, this really has me scratching my head.

It's highly unlikely that any relay is going to be activated with just a diode drop across it, right? So, the only way I see it switching is if the zener side is more positive than V+. But how can that happen?
 
DC offset ... failure scenario
not a delay turn on / soft start
but I don't think it looks like the typical mods for the Phase Linear 70's stuff.
why is it on the other side of the diode ... halfwave ?
power rail monitoring ?
:roll:
relay is closed when there is a level of power rail but if the output DC rises to ??? it opens ....

why am I having trouble with this ... is it the way it is drawn ??

arrgghhh ... :sad:
stupid Kev ... have another coffee.
 
Well, at least those shorted emitters gave me an idea. What if I put a pair of RC time constants across the bias references in my buffer?

Like this (in red):

buffer-anithump.gif


This would turn the biasing to the subsequent stages on slowly as the supply powers up, avoiding any potential thumps if I happen to use this as a power amp. Look like it will work? Common thing to do?


I just finished my 3rd coffee for the day. :wink:
 
Or even more similar to the shorted emmiters idea:

buffer-anithump-2.gif


Micro-Cap analysis shows that it does shut off the subsequent stages while the capacitor impedance is low.

Good idea? Bad idea?
 
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