Wow! Thank you PRR, this is exactly what I was hoping for. Did you sim this out? Or is this all just on paper/in your head?
[quote author="PRR"]> sine wave on the input and clip the circuit, bias until its symmetrical.
Why?
The circuit will pull up to nearly +24V, down to nearly +0.6V. The "ideal bias" might be +12.3V on the output node. However if signal is within 10% of maximum output, you don't want a bias trim, you want a smaller signal or a higher rail. So +/-10% tolerance on the output node voltage is entirely acceptable. I'd be happy 10V to 14V.
What IS the voltage on the output node? It follows the Q1 Gate voltage except a bit higher. The "bit" is the G-S voltage of Q1 at the operating current. How much is operating current? Well, if Q2 is working at all happy, its Vbe is 0.6V-0.7. Assume for a moment that Q2 has high Beta and low base current. Then R8 must drop ~0.7V, almost entirely due to Q1 current. Therefore Q1 must pass 0.7V/11K (11K?) or 0.06mA to make Q2 happy by pulling Q1 Source up a "bit" above its Gate voltage.
Digression: Q1+Q2 current is Q3 current. Q3 is set to pass 0.7V/100 or 7mA. Q1 was assumed to pull 0.06mA. So Q2 should pull 7mA-0.06mA= 6.94mA, essentially 7mA. Q2's type is not specified, but at 7mA and 12V or 24V it probably isn't a "power" type, so we can assume Beta is 50 to 500. Then base current is 7mA/50 to 7mA/500 or 0.14mA to 0.014mA. This plus R8 current (0.06mA) must flow through Q1, so it passes 0.06mA+0.14mA= 0.2mA to 0.06mA+0.014mA= 0.074mA. [/quote]
I will have to read this over several times, but I think im starting to see all the current/voltage relations between Q1 + Q2. One thing i didn't realize at all was that with a lower Beta there is a higher base current draw.
[quote author="PRR"]>A JFET is somewhat like a vacuum tube. The gate-source voltage determines the current, there is a maximum current (Idss) for zero Vgs, there is a voltage which will cut current to near-zero (Vth). Idss for jellybean JFETs is 2mA-20mA, and we will pass 0.2mA or less, so Vgs won't be zero. It will tend to be near Vth, often called Vgs(off) on datasheets (Vth Threshold is a concept, Vgs(off) is actually a specified test where "off" really means some small current like 2nA). This voltage is very poorly controlled, and can range from 1V to 8V. In practice, I'd bet on our ~0.1mA current biasing to 2V to 4V G-S in 90% of samples. [/quote]
The circuit I first saw in this configuration was a jfet input so I stuck with that, but i've always assumed that JFET usually had a higher input impedance than BJT, I think because usually it's that way in opamps. Is that true?
I was thinking of trying the venerable 2sk170BL in this circuit, either way it seems i may have some jfets that just dont work because they have too low Vgs(off). If I can do a test jig where i can test what my Vgs(off) would be, I could do a general sort of matching like that. That wouldn't take too long (not much longer than biasing, thats for sure!) or be too expensive to do.
[quote author="PRR"]>Then to get 12.3V at the output, we set the Gate 2 or 4 volts higher, say 15V. The output node may really come out at 11V or 13V, who cares? In extreme cases it could be 15V or 7V.
The ideal 12.3V output bias gives 11.7V swing. A 7V output bias gives 6.4V swing. Your choice to trim this or select middle-spec JFETs. Trimmers fail a lot. JFETs are cheap enough to throw-out a few oddballs, though testing (OR trimming) is extra production expense.
Your 1Meg(?), 47Kvar 820K bias scheme gives less than +/-1V adjustment. In fact if you are within 1V you are good to rock; but production JFETs may be in a 4V or 8V range. Either give yourself more trim, or see if you really need a trim at all. If your signals are guitar they will never be over 1V peak, if hi-fi then probably 2.8V peak, so a bad-trim 7V peak swing amp is not getting in your way and a perfect-trim 11V peak amp is no better (certainly not worth a trim or selection). [/quote]
This is what I most took from this post, i'm way to used to tube guitar amps where players frequently just dime it out and go for broke. This concept of designing each stage to stay below clip referencing the input is something I never fully considered here. And it makes perfect sense - a single stage never seeing more than a volt will not clip a 24V system. even with a distortion pedal it wont doit, AND the preamp the circuit is feeding + the input TX will clip prior to any of this circuit clipping.
[quote author="PRR"]>BTW: Q1 could be a BJT, you would know the Vbe within +/-0.1V, you'd set the Q1 base at +13.2V for "perfect" or at 12V because it works the same and uses equal resistors. Yes, a clean silicon BJT at this current with this much NFB stuffed up its rear can have a input signal impedance far over 1Meg. [/quote]
I should try it with a BJT for sure, can you recommend a good sounding reliable one?
[quote author="PRR"]>understand solidstate better.
Put a long (capacitive) cable on the output. Put a large fast transient (squarewave) on the input. What is the peak current in Q2? By Ohms Law, about 10V divided by nearly zero ohms (there's no explicit resistance from rail to load) or roughly infinite current. Even if we assume an ohm in Q2 and another ohm in the cable before most of the capacitance, it's like 10V/2= 5 Amps. You can do a lot of medium-hard benchtesting without failure, yet have a mysterious Q2 death with slightly more drive/load, or worse: mystery Q2 failure on-stage where signals and loads are sometimes quite crazy. And that's stuff you WON'T see in any sim (unless you know systems well enough to ask and understand the right questions).[/quote]
Ok so basically what is happening is Q2 is seeing a shorted load in high frequency and when its input is high frequency, blamo - it over works itself quite fast. This circuit's main function is going to be feeding an input transformer primary - which is around 150ohm impedance, but no long cables with high capacitive loads. That being said, i'd like the circuit to work in other situations aswell and i'd like to understand what I could do to prevent that scenario from happening. So what I need is to limit the current that Q2 can draw through its load to the rail.
Could I put resistance between the output node and Q2's collector to limit the its current draw? Maybe around 500ohms or maybe more?
I guess I could put resistance from the rail to emitter, but something about that idea feels strange. I have no clue what, but it just doesn't seem right.
Do I have any other options? I'm assuming limiting the current is the way to prevent the 'mystery death' but maybe not... I just don't have the experience in design aspects to know for sure.
Looking forward to seeing where it goes from here, i'll start by ordering some parts to breadboard this out with.
Thanks!
