Increasing current capacity for capacitance multiplier circuit

[DaveDC]

I don't know if it actually matters but R6/C3, R3/C2, etc, are all reversed in relation to ground when compared to the schematic I posted above.

The order of components in series doesn't matter electrically. I drew them this way to convey the design intent: caps to ground with ESR.

 

[DaveDC]

You appear to have an ac sine source driving a 200uF capacitor directly which will mess with the ac analysis. You need to set its source impedance to some non-zero value .

I am not sure why you are using a current load. Try using a resistor instead.

Cheers

Ian

QSpice is adept at handling this case when calculating the operating point on the first simulation pass. From there, the nonlinear circuit is linearized, then the small-signal analysis is done. But I believe you so I checked; the simulation is identical with the caps deleted.

The current source load was used for the simulator to establish a known load current when calculating the transistors' dissipation. OP wanted to explore increasing the current capability, so I had to pick some load current. But since the circuit has really crummy load regulation, resistive loads would give different dissipation readings for the two transistor comparison cases because the output voltages would be different. But I checked that too and found the sim was identical with 6 ohm resistive loads.

As I think about it, many commonly encountered loads (opamp rails, etc.) behave like current sinks, not resistors. Most electronic loads support constant-current loading as well.

 

[Matador]

I did a quick simulation of that circuit, and a few things popped out that are strange.

First, under DC conditions: the base of Q2 charges up to 98% of the input voltage (15V) through the RC divider between R2+R4 and R5. This is 14.7V. With Q2 'on', the output should sit at a constant VBE drop below that, or about 14V.

If there is 1V of ripple on the input (superimposed on the 15V), when the input voltage drops to 14V, the base is still held at 14.7, however the emitter is still at 14V, so the collector voltage drops down towards 14V, since it can move faster than the base. This turns on the base to collector diode, causing a spike downwards in the base voltage until the base node discharges back down to below a diode drop. This cycle repeats, leaving a very noisy output as Q2 switches on and off.

I think if you want to use this circuit with any significant ripple on the input (any ripple in excess of a junction diode threshold), then the base voltage needs to be lowered, so that worst case, the base will always be at least less than a diode drop to the collector. Raising R2 and R4 up to 6.8K, causes the output to lower to 13V, giving 1V of margin to 1V of input ripple. After raising R2 and R4 up, I see a clean output and about 70dB of attenuation from input to output (or it converts 1V of input ripple into 3mV of output ripple).

 

[Cqwet Dbdfte]

QSpice is adept at handling this case when calculating the operating point on the first simulation pass. From there, the nonlinear circuit is linearized, then the small-signal analysis is done. But I believe you so I checked; the simulation is identical with the caps deleted.

The current source load was used for the simulator to establish a known load current when calculating the transistors' dissipation. OP wanted to explore increasing the current capability, so I had to pick some load current. But since the circuit has really crummy load regulation, resistive loads would give different dissipation readings for the two transistor comparison cases because the output voltages would be different. But I checked that too and found the sim was identical with 6 ohm resistive loads.

As I think about it, many commonly encountered loads (opamp rails, etc.) behave like current sinks, not resistors. Most electronic loads support constant-current loading as well.

LTspice has capacitor models with parasitics, QSPICE, have not found them, you have to add them all manually. Electrolytics would not be very good at high frequencies, with minimal rejection already the circuit seems like a waste of time and space.
The output voltage is dependent on transistor beta, so the circuit is basically a current source not s voltage source, so expect load dependent voltage output.
Consider AD silent switcher® for low noise and low heat generation.

Even the old 3-pin LDO LT1085 (or even the LT1764A) had 60 - 80 dB rejection up to 10kHz if you want to use a heatsink.

 

[DaveDC]

I did a quick simulation of that circuit, and a few things popped out that are strange.

First, under DC conditions: the base of Q2 charges up to 98% of the input voltage (15V) through the RC divider between R2+R4 and R5. This is 14.7V. With Q2 'on', the output should sit at a constant VBE drop below that, or about 14V.

If there is 1V of ripple on the input (superimposed on the 15V), when the input voltage drops to 14V, the base is still held at 14.7, however the emitter is still at 14V, so the collector voltage drops down towards 14V, since it can move faster than the base. This turns on the base to collector diode, causing a spike downwards in the base voltage until the base node discharges back down to below a diode drop. This cycle repeats, leaving a very noisy output as Q2 switches on and off.

I think if you want to use this circuit with any significant ripple on the input (any ripple in excess of a junction diode threshold), then the base voltage needs to be lowered, so that worst case, the base will always be at least less than a diode drop to the collector. Raising R2 and R4 up to 6.8K, causes the output to lower to 13V, giving 1V of margin to 1V of input ripple. After raising R2 and R4 up, I see a clean output and about 70dB of attenuation from input to output (or it converts 1V of input ripple into 3mV of output ripple).

You are right, Matador. My setting the AC analysis amplitude at 1 volt was a simulation mistake on my part. In OP Paul's SMPS filtering application, 1 volt of input ripple is unlikely, so I changed the AC amplitude to a more realistic 100mV. I tried increasing R2 and R4 as you suggest, and it does improve the filtering for the BD140 case but doesn't change the 2AS2222 case much. But it dramatically increases the dissipation of the pass transistors. So the original circuit with a higher gain pass transistor would be an improvement, keeping in mind as you noted that the circuit has a limited input ripple amplitude range.

 

[DaveDC]

LTspice has capacitor models with parasitics, QSPICE, have not found them, you have to add them all manually. Electrolytics would not be very good at high frequencies, with minimal rejection already the circuit seems like a waste of time and space.
The output voltage is dependent on transistor beta, so the circuit is basically a current source not s voltage source, so expect load dependent voltage output.
Consider AD silent switcher® for low noise and low heat generation.

Even the old 3-pin LDO LT1085 (or even the LT1764A) had 60 - 80 dB rejection up to 10kHz if you want to use a heatsink.

Agreed that this is a crummy circuit compared to any closed-loop regulator, linear or switching. Just helping OP appreciate the dependence on beta as you pointed out.

BTW, like LTSpice, QSpice passives support a number of instance parameters including series resistances. You just add them when declaring the component value, i.e. "22uF RSER=1" I'm pretty sure that when Mike Engelhardt wrote QSpice, he included all of the functionality of his prior program LTSpice. The UI is really different, though, so I'm finding it a bit difficult to find all of the features.