Pots in Series

[Phrazemaster]

I am not sure I want to open this can of worms... BUT it is not because I value my IP so highly, but I prefer teaching people how to solve their problems, more than just giving them the answers.

It is also a minor PIA for me to scratch out a schematic (involving different computers), so I generally don't I worry you did not get the concept I offered. Making a coarse and fine adjustment with two pots means the fine adjustment needs to have its sensitivity reduced. An easy way to do that is with a resistive divider between the two wipers (lower impedance in series with coarse wiper, higher impedance in series with fine wiper) .

In fact there are probably a half dozen workable solutions for this problem. If you don't care how to do this, but just want a solution (sounds like management material) I'm sure one of the solutions offered by a more helpful forum member will work.

JR

Hi JR,

Thanks for taking the time to share.

Yes I do care to understand - my god I've spent so much time/money on stupid parts trying to figure this out! I would be embarrassed to tell you how much of each. And of course googling and using my noodle, such as I can.

You've given me a good hint, now with additional info. I appreciate that and will see if I can come up with what you are talking about. I'm just not the brightest bulb when it comes to electronics - although I am fairly good at being creative with many other things. But I love making things, which is why I'm hooked on DIY. And I love the challenge of figuring things out, which is right where I am at this point!

And no, I don't just want an answer - I would like to understand it!!! Although I may at some point just give up this puzzle as I do need to actually finish this little FET tester!

Much respect and appreciation for your time and thoughts. I'll see what I can do.

And thanks to everyone else, PRR, Magneto, BlueBird!!

Mike

PS I'm posting a little pic of the tester in its not-quite-finished state, but you get the idea. Thx.

 

[Phrazemaster]

Rear.

 

[bluebird]

Lol, thats awesome...

 

[JohnRoberts]

Hi JR,

Thanks for taking the time to share.

Yes I do care to understand - my god I've spent so much time/money on stupid parts trying to figure this out! I would be embarrassed to tell you how much of each. And of course googling and using my noodle, such as I can.

You've given me a good hint, now with additional info. I appreciate that and will see if I can come up with what you are talking about. I'm just not the brightest bulb when it comes to electronics - although I am fairly good at being creative with many other things. But I love making things, which is why I'm hooked on DIY. And I love the challenge of figuring things out, which is right where I am at this point!

And no, I don't just want an answer - I would like to understand it!!! Although I may at some point just give up this puzzle as I do need to actually finish this little FET tester!

Much respect and appreciation for your time and thoughts. I'll see what I can do.

And thanks to everyone else, PRR, Magneto, BlueBird!!

Mike

PS I'm posting a little pic of the tester in its not-quite-finished state, but you get the idea. Thx.

Good answer...

OK here is an slightly easier version...

Add a second 100k pot in parallel across the first one.

Connect the wiper of the second (fine trim) pot through say a 100k resistor to yhr first wiper that is also connected to the JFET gate.

Center the fine trim pot, and use the coarse trim pot for rough adjustment, then fine tune with the fine tune pot.

Easy peasy....  this is a little squirrely if the coarse pot is at one extreme or the other but otherwise should work...  A second resistor in series with the coarse wiper solves that, but this is simpler and should work OK.

JR

 

[Phrazemaster]

Good answer...

OK here is an slightly easier version...

Add a second 100k pot in parallel across the first one.

Connect the wiper of the second (fine trim) pot through say a 100k resistor to yhr first wiper that is also connected to the JFET gate.

Center the fine trim pot, and use the coarse trim pot for rough adjustment, then fine tune with the fine tune pot.

Easy peasy....  this is a little squirrely if the coarse pot is at one extreme or the other but otherwise should work...  A second resistor in series with the coarse wiper solves that, but this is simpler and should work OK.

JR

I think, despite my best efforts to remain ignorant, the light is dawning. I'm going to implement what you suggested JR, and later tonight I'll draw a schematic. You don't have to tell me if I got it exactly right, but you could kind of wink at me or say "it will work" if I'm close, er, something?

Thanks much, to you and everyone. This place because of y'all is so great!!!

Mike

 

[Phrazemaster]

OK, I think I've got the course/fine pots working!!! Attached is schematic, and it works very well for adjusting the voltage coursely, and finely!

What do you guys think?

I'm still having 2 challenges.

1) Now the  AC voltage at V doesn't drop when the gate voltage drops - this was working fine when I used a single pot. It basically means the FET tester doesn't work, even though the gate voltage is now very easy to control. I double checked connections;  the only change was to implement the dual pot scheme

2) I had a regulated power supply giving 9 volts, and now with the dual pots it goes only as high as -8.2 volts. I'm not actually sure this is a problem, if all FETS are tested with the same starting voltage, but what do you guys think?

Thanks a zillion to JR, PRR, Magneto, Bluebird and others who helped.

Mike

EDIT: I unplugged/replugged everything, and now it seems to be responding as expected with the mV at point V falling when gate voltage falls. Not sure if I have a cold solder joint or what, so I'll watch it. Still not sure about only having rougly 8v on the gate at max setting though - any thoughts?

Thanks again Gents!

 

[PRR]

> FETS matched using the -9V on the gate

Almost all JFETs will be HARD-off at -9V on the Gate.

"Switch" JFETs may be -4V or so. "Amplifier" JFETs may be -2V roughly. Some are routinely under 1V.

You said it was "twitchy" so I thought you needed MUCH less than a 0-9V range.

What are typical numbers for those 10%, 50%, 90% points?

Or maybe your pot is dirty, can't get/hold a setting.

 

[Phrazemaster]

Here's the numbers I'm getting. The AC mV numbers from the Sig Gen bounce around constantly, but when I connect only the DMM to the Signal Generator the AC mV numbers are steady. It also means it's very hard to get an accurate reading as the numbers jump around sometimes within a mV.

Here's some typical numbers, in the attachment. I couldn't get things to line up in plain text here sorry.

Thanks kindly.

Mike

PS I bought a 15v input supply so am able to get the original numbers closer to -9v for measuring. Although not always lol.

 

[MagnetoSound]

I had a regulated power supply giving 9 volts, and now with the dual pots it goes only as high as -8.2 ... any thoughts?

I suppose the likely answer is that the 50k load presented to the supply by the paralleled pots is enough to drop the voltage at the supply.  Try higher pot value?

If you increase R5 you will lighten the load on the sig gen too.

 

[Phrazemaster]

I suppose the likely answer is that the 50k load presented to the supply by the paralleled pots is enough to drop the voltage at the supply.  Try higher pot value?

If you increase R5 you will lighten the load on the sig gen too.

Thank-you Dan - excellent suggestions.

 

[Phrazemaster]

Here was the first version...

 

[Phrazemaster]

So here's a question - what might make the mV readings jump around a lot?

I have the little unit with no power - so the DC power Supply is out of the equation completely.

I have no transistor in the sockets.

Yet the mV readings from point V to ground fluctuate within a mV, very quickly.

When I hook up the DMM directly to the signal generator, there is no fluctuation.

Any thoughts?

Thanks,

Mike

PS the schematic is as-posted above.

 

[Phrazemaster]

OK I start to answer my own question - physically removing the power supply cord makes the readings totally steady. So it's  some AC in the power supply. Specifically around 1.4mV

And this shows up only with plugging in the cord, not even turning on the circuit.

I have a wall wart putting out 15v regulated. It's inputting into the back of the tester, with a small variable regulated supply with an LM317 and a trimmer to get exact output.

I have a .1uF across the input, and a 1uF across the output of the regulated supply in the tester. Attached is the exact circuit I'm using, right out of the TI datasheet. I am using a 120R resistor instead of a 240R, note.

I thought putting the caps in would remove residual AC from the output?

I know this is Electronics 101, and I'm in this to understand it at this point. It's become my franken experiment.

Any thoughts?

Thanks,

Mike

 

[Phrazemaster]

So it appears the PSU wall wart was providing the mystery AC mV noise. I strapped a .1uF capacitor across input/output, along with a 1.5K resistor to make a little low pass filter, and the readings are now VERY stable! They still move around a little, but they stay still for seconds at a time - totally useable.

Only, that ate up more needed power, so now I've got only -7.51 volt at the gate. Geez. I had bought a 15V PSU wall wart and it is unregulated, so I was getting less power under load. Looks like I need to go to an 18v supply. This has gotten ridiculous. I guess the original plans with the battery were best; it's just that the voltage was dropping over time since it was a battery.

I spent a few hours on all this silliness today on Thanksgiving. I'm grateful for all you incredible guys out there! I've learned more about FETS, power supplies, noise, and making stuff in the last couple weeks with this little fun circuit from PRR!

Happy T-day gang!

Best,

Mike

 

[MagnetoSound]

Sounds like your PSU needs to provide more current, not more voltage.

If you beef up the supply, you will get less ripple and eliminate the voltage drop. 18v is a bit mad for a 9v circuit. Stick with 12-15 volts, but you might need a good few hundred milliamps, even 1 amp, of rating to get a sensibly stable output across a variety of load conditions.

Keep the filter/smoothing caps at the box for good measure. (The regulator doesn't hurt either, since you've already done it, but I would prefer a regulated input with good current capability outside the box over something bouncy and trying to fix it.)

 

[Phrazemaster]

Sounds like your PSU needs to provide more current, not more voltage.

If you beef up the supply, you will get less ripple and eliminate the voltage drop. 18v is a bit mad for a 9v circuit. Stick with 12-15 volts, but you might need a good few hundred milliamps, even 1 amp, of rating to get a sensibly stable output across a variety of load conditions.

Keep the filter/smoothing caps at the box for good measure. (The regulator doesn't hurt either, since you've already done it, but I would prefer a regulated input with good current capability outside the box over something bouncy and trying to fix it.)

Thanks Magneto.

The wall wart power supply claims to go up to 2A at 15v but clearly that was marketing! I'll look for something better. But I was really hoping to avoid making a full blown PSU, with a transformer and rectifier etc. I mean I can, but it seems so incredibly overkill for this. I was hoping for a decent wall wart supply that would be enough for testing a FET.

Question: I see some of these newer "switching" power supplies. Will this introduce additional AC noise on the DC output?

Thanks Kindly,

Mike

 

[MagnetoSound]

Sorry Mike, I think I may have led you up the garden path ...

9v into 50k is only 0.18mA! Where is all the current going??

Perhaps a DC blocking cap is needed at the sig gen - if it doesn't have one internally (it oughta) then there is current going astray there, which might explain it going a bit doolally.

Either that, or you keep testing a shorted FET?

Hope this helps, I'm running out of ideas now ...

Can you check mA at the sig gen output, and the psu output to find out what is dropping the volts?

 

[Phrazemaster]

Sorry Mike, I think I may have led you up the garden path ...

9v into 50k is only 0.18mA! Where is all the current going??

Perhaps a DC blocking cap is needed at the sig gen - if it doesn't have one internally (it oughta) then there is current going astray there, which might explain it going a bit doolally.

Either that, or you keep testing a shorted FET?

Hope this helps, I'm running out of ideas now ...

Can you check mA at the sig gen output, and the psu output to find out what is dropping the volts?

Yes great ideas! Thx!

The FET  gets very hot. But I’ve tested many and they all do. Yes this doesn’t make sense does it.

I noticed a lot of DC on the sig gen output, if memory serves over 4 v. I’ll verify that so don’t take that as truth yet.

I’ll go back to it. The truth is out there.

I’ll let you know what I find out tomorrow.

Thank-you!!!

 

[Phrazemaster]

Now wait a minute something else funny I had noticed.

The leads on the signal generator had to be put with positive and negative a certain way or the whole circuit doesn’t work (the sig gen has a ground and a signal lead).

This made no sense to me - it’s AC. So maybe there’s a ton of DC at the sig gen output.

How would this affect the circuit and FETs? Might it cause the results I’m seeing?

Thanks.

 

[MagnetoSound]

That sure sounds very suspicious.