pseudorandom binary sequences with nonzero mean

[bcarso]

The standard hardware generator for pseudorandom binary sequences is a shift register with feedback from various taps going to XOR gates with their outputs fed back to the input. The mean value of voltage over a whole sequence of states before repeating is the average of the low and high logic voltages. For audio use typically CMOS stages with equal magnitudes of Vdd and Vss are used so that the average d.c. output value is about zero.

Before doing a lot more reading and thinking I thought I'd throw out the question in here: is there a way resembling the shift register approach that could be set for sequences with various mean values differing from zero?

 

[mjk]

The LFSR will I believe always be biased slightly toward the "one" output because there is no state with all zeros. I think any maximal length sequence LFSR has this property as it is periodic and will cover all states except all-zeros.

Are you trying to create a pseudorandom sequence intentionally biased toward one or zero, i.e. more ones or more zeros in the output stream? You could take an LFSR output stream and manipulate the output by adding a "constant". I don't know if that's what you're after...

Michael

 

[Samuel Groner]

Probably not possible--ain't these sequences aimed for having white spectrum?

Samuel

 

[jdbakker]

The easiest way is to feed a number of bits from the LFSR to a digital magnitude comparator, and use the comparator's '<' output as your level-shifted noise sequence. This is akin to dithering a DC level with a rectangular dither.

In most CPLD families a magnitude comparator with a fixed constant on one of its inputs is reasonably cheap resources-wise; if you want/need to go discrete a 74HC85/74HC682 or similar will do nicely.

JDB
[if you need the output to be 'white', you may want to simulate this setup and run an FFT over the results]

 

[bcarso]

Thanks for all those comments. Yes, as mjk points out, speaking precisely there is a bias, because of the one prohibited lock-up state. This gets as small as we like with longer SRs.

I don't care if the noise is exactly white, and I realize that some of the criteria for mimicking a true stochastic process will probably not be met. JDB's suggestion is probably workable and likely the most elegant for my needs.

What I'm after is something to use as a modulator for PWM resistors in a filter application. I'm concerned about heterodyning artifacts that might be generated downstream with one or another variety of switchmode amplifiers.

I'm thinking that a bit of extra noise as the effective artifact would be far more tolerable than whistles and tones.

Now, one can work out how to synchronize the pwm resistors to the switchmode amp, possibly, in the case of the more conventional fixed-freq pwm; then you have the likelihood of offsets at some level, but these can be highpassed out---as long as the variation in the PW is reasonably slow, which it would be in this case. If the switchmode amp is variable frequency then things get more complicated.

And then there's just the notion of keeping the system sufficiently clean and lowpassing or otherwise comb-of-notches filtering the filter outputs ahead of the power amp. But my experience has been that once you start listening for things it's amazing how deep into the noise you can detect them.

The PWM resistor approach to varying filter parameters was used in an old JBL-branded aftermarket-automotive line-level crossover product years ago that Brad Plunkett assisted Robert Girard with in development. The pwm approach was mainly an expedient to allow single-section cheap pots to vary a multitude of channels of filter. It worked reasonably well, although in its day the class D amplifier it might have fed was a rarity.

 

[bcarso]

And here's another related question: is it feasible using tight code in a general purpose uC to generate a few streams identical to the LFSR and hardware digital comparator's < output? Let's say we want a SR clock frequency of a few hundred kilohertz.

EDIT: and I'm supposing that the uC is not doing a bunch of other system housekeeping chores...

 

[jdbakker]

[quote author="bcarso"]And here's another related question: is it feasible using tight code in a general purpose uC to generate a few streams identical to the LFSR and hardware digital comparator's < output? Let's say we want a SR clock frequency of a few hundred kilohertz.[/quote]
It Depends.

For audio work you'd want the period of the LFSR to lie outside the audio band (at the very least). With a clock of a few hundred kHz that's an 18-bit register or better; take 23 or 24 bits as that is just as easy for an uC. Depending on your processor's instruction set I'd say a typical eightbitter can run a single 24-bit LFSR + comparator + I/O in a dozen or so instructions.

Now, a 24-bit LFSR may still have periodical audible artefacts, especially when your control value is near its extremes. Go 32-bit, with a repetition rate of an hour @ 1MHz, and you'd be safe from those too. If you need several such streams I would suggest giving each a separate LFSR polynomial to reduce interactions (and make sure the LFSR lengths are unequal and ideally relatively prime). That would make any of the ARM7 uCs an ideal choice, as they can do a 32-bit shift/XOR/compare/IO cycle in five instructions (assuming all registers are preloaded).

Plan C: Use a large NOR Flash chip plus a counter.

JDB.

 

[bcarso]

Yeah, I have worried a bit about the extremes of the range, as well as the audibility of the rep rate. The Ap generator used to irritate me by sounding like some kind of steam engine, given the very audible repeats.

This approach is mainly conceived as being a vernier on non-modulated switched values of R. For that matter I could just add more adjustment bits and Rs and switches and make the whole thing static, but this sounded like fun. It might be well to have two modulated Rs so neither has to go too close to zero or 100%. But then that is getting complex. It might even be acceptable to have small gaps in the adjustment range for this particular application.

I figured it was do-able with a decent late-model micro, but since I defer code generation to subcontractors I figured I would ask in here first. Lately one of the best ones has been getting a bit lazy and using compilers, although in his defense it was entirely appropriate for the particular task at hand, and way easier for someone else looking at the source code to maintain.

Supposedly the people I will be working with are veritable whizzes with uC. We shall see.

 

[mikep]

spread spectrum PWM, very interesting. but IMO it doesnt sound like the right solution to your stated abjectives. to eliminate heterodyning wouldn't it be much simpler to syncronize all the PWM stages to a common clock? if you are worried about PWM signal bleedthrough perhaps selecting a higher (fixed) frequency clock will make it easier to filter to the desired extent? (assuming all your analog signals of interest are at frequencies lower than the PWM clock.)
sorry if that is obvoius and boring input.

[quote author="bcarso"] but this sounded like fun. [/quote]

Indeed, Id like to see where this leads. Im scratching my head trying to figure out what problem, if any, spread spectrum PWM hits square on the head. Its got to have some benefit other than making the switching signal noise-like. up till now this has been used for EMI reduction purposes only?

mike p

 

[bcarso]

Mike, note that I do mention fixed freq operation synchronized to the amplifier above (and thus different switches synced as well). That is straightforward, likely to produce small offsets which are probably tolerable. And it may be a satisfactory approach. This is a what-if speculation to some extent.

It's interesting to consider JDB's approach at the extremes. Clearly, right before you hit 100% or 0% duty-cycles you are getting the equivalent to a conventional fixed-freq pwm output, that is, spectrally a line spectrum with integer-multiple spacing. But with a long repetition period this would be perceived as a little tick, not as a tone.

As you move away from the extremes things get more complex in a hurry.