On the connector (2-row, 64-pin 'VME-style' DIN connector):
host address port = A30,B30,A29,B29...B27 = A0..A7
On the DSP card, the littlest address bus bits go to the three bits of the DSP host address bus. I suspect that the upper nibble of the address bus is used to decode the card address. There is a latch for the card address.
host data port = A26,B26...B23 = D0..D7. On DSP card, this goes to the 56002 DSP, I will presume that on the ADA card, it is buffered then goes to the audio level DAC's.
card present = A22 (open-collector)
host bus/address enable (active-low) = B22
host read/write (write=low) = A21
host request (from 56002 DSP) = B31
audio running? = B32, stays low until init is done, then goes high
ground = A20,B20,A5,B5
+5V = A4,B4
-5V = B3
+27V = A2
-27V = B2
audio data bus = A18...B7 (24 bits, D0..D23). Data is active just after the falling edge of clock A19, and goes inactive just after the falling edge of clock 6A. Stereo data appears to be how you would expect. Time slot 0 audio data (say, left) has a corresponding opposing audio data at time slot 32 (say, right). I do not know which is left or which is right yet.
audio data clock (64 Ts) = A19
audio data sync (Ts) = B19, active-low, pulse is in phase with A19, and is active for 1/128 Ts (ie. is low while A19 is low)
audio data clock (64 Ts) = A6, leading A19 by 90 degrees
master clock (256 Fs) = A3, 12.288 MHz if the input signal is 48kHz. Use as MCLK for a CODEC.
And the two signals I'm not certain of...
unknown, has little pulses on it = B21 - goes to decoder PAL pin 2 (input to card)
unkown, goes to decoder PAL pin 3 = A31 (input to card)
I do not know if the host is used to assign the ADA to a time slot or if that is done simply by address (ie. hardware on the card just picks whatever time slot to read and/or write from). I would almost expect the audio to go from ADA to DSP in, say, time slot 0, then from the DSP to the ADA in the next time slot... or possibly time slot 8? I am assuming this because with the use of the HC299 parallel/serial shift registers, this is the logical thing to do - you use one set of shift registers for both parallel-to-serial and serial-to-parallel conversion. An offset of eight makes more sense from a clocking perspective, given that there are 32 bits per cycle, and a 24-bit shift register.
Just in case anyone wanted to know the pinout of the TC mainframe connector... The audio appears to show up as 64 time slots of parallel 24-bit data, from what I can tell.
With a bit of trial-and-error, it should be possible to reverse-engineer the last little bits, first with a wire-wrapped prototype card and enough digital logic to 'fake' an ADA card's digital/bus portion. Once that is decoded, the CODEC could be added to the design, and the whole thing put on a PC board.
-Dale
