Looked at some XMOS TDM examples (xmos/lib_i2s on Github) where they have used CS4384 DAC, and the CS4384 datasheet says:
The TDM serial audio interface format operates in Single-, Double-, or Quad-Speed Mode and will slave
to SCLK at 256 Fs. Data is received most significant bit first on the first SCLK after an LRCK transition
and is valid on the rising edge of SCLK. LRCK identifies the start of a new frame and is equal to the sample
rate, Fs. LRCK is sampled as valid on the rising SCLK edge preceding the most significant bit of the first
data sample and must be held valid for one SCLK period.
So they are using LRCK and SCLK signal names, and let us know that the LRCK must be valid one SCLK period before first data bit. Maybe they haven't just tested their software with other TDM input DAC's which don't have that one sample period offset.
Seems they have also changed the architecture of I2S/TDM lib from sample based to frame based at some point to save processing time.