1176 Rev A Circuit THD problems, Impedance balanced vs electronically balanced source

[jonathanmorbin]

Hi Everyone,

So I have an issue that I cant seem to understand why its happening and was hoping someone might have some ideas as ive been doing so many tests and cant find any conclusive answers!

I have a 1176 Rev A circuit that I made and works great, however I noticed that I was getting slightly higher than expected THD from the FET gain reduction circuit. Around 1.5-2% as opposed to the expected 0.5%. Im running a signal out of my DAW using a my SSL Alpha link convertors and during testing I tried it with my RME Madiface and the THD reduced to the expected 0.5%. Now the only difference between these two setups is that the Alpha link is an impedance balanced output and the RME is electronically balanced.

Can anyone tell my how this could be effecting/interacting with the FET GR circuit?

Im pretty sure ive narrowed it down to only this difference with all my testing. When the FET is not biased there is no difference in THD readings between the two outputs. Its only when the FET is biased that the different THD readings occur so it seems to be something interacting with that part of the circuit.

I have an older version of a REV A Hairball unit which doesn’t seem to be affected at all by the two different output types so I have been using this a lot to compare and try to narrow down. Ive also noticed that raising the value of C6 which is across the control voltage resistor going to the FET makes a difference to the THD on the unit in question. However it seems to make it better for the impedance balanced output and worse for the electronically balanced!

My only thought is its something to do with how the input is interacting with grounding as the FET is connected directly to ground in this version of the circuit? But im really scratching my head at the moment!

 

[ccaudle]

the only difference between these two setups is that the Alpha link is an impedance balanced output and the RME is electronically balanced.

Will need some more confirmation before taking your word at that.

Have you measured across pins 2 and 3 at the 1176 input and verified that the levels from each interface are within a fraction of a dB of each other? Symmetric drive could have 6dB higher output (i.e. double the voltage), which could increase distortion.

The specs of the MADIface XT indicate maximum output level of +15 dBu while the SSL AlphaLink indicates a maximum output of +24 dBu. A 9dB lower input level would be expected to reduce distortion.

 

[jonathanmorbin]

Yes I matched the two levels. They measure the same across pins 2 and 3. And I made sure they measure the same after there input transformer too just before it enters the GR circuit.

 

[ccaudle]

Yes I matched the two levels. They measure the same across pins 2 and 3. And I made sure they measure the same after there input transformer too just before it enters the GR circuit.

Perfect, that eliminates level differences as a cause.
The next verification I would do is run a parallel connection, connect the interface with higher distortion to the 1176 input, and either using a y-cable or by soldering a pair of wires to pins 2 and 3 on the 1176 input connector run to your interface you use to measure distortion. The goal with that connection is to see if the distortion is occurring in the output stage of the audio interface. Perhaps the loading of the transformer in the 1176 is causing some strange behavior.

What is the turns ratio on the input transformer? The 1176 rev A schematic I found has a 270 Ohm resistor across the secondary. I could not find an explicit statement of turns ratio, but did find a document which showed the transformer as a 500 Ohm:200 Ohm transformer, which would make that 270 Ohm secondary load about 675 Ohms on the primary. That is a pretty heavy load for a modern output stage, you could conceivably get couple percent THD if an output was designed expected a couple of k Ohm minimum and connected it to a 600 Ohm load.

 

[jonathanmorbin]

So I initially noticed the distortion with a DAW plug in however I have now moved to probing the circuit with the Qa401 analyser. I am measuring the distortion now at C7 just after the preamp circuit. I have checked the XLR input, After the Input attenuator and right after the input transformer and all is clean. It's once it touches the FET (2n5457) that the distortion occurs and as I mentioned only when the FET is biased. I have tried changing the FET and making sure all the components around that part of the circuit are correct. I have even tried adding a simple unity gain NE5532 input buffer just after the XLR on pins 2 and 3 to see if this made a difference and it didn't.

I am using the Sowter 1260 input transformer:
https://www.sowter.co.uk/specs/1260.php
And a custom 3 deck Omeg input attenuator, 470Lin:1klog:470Lin

I have the same parts in my MNATs version which is clean with both inputs and I have switched around all the parts in the input section to make sure its not an out of spec part there. Main differences between the MNATS version and the one in question is that the MNATS has a lot of off board wiring, for example the input xlr is chassis mounted, grounded directly to the chassis with all the input circuit off board until it hits the 270r resistor. Where as the one in question has XLR's, input attenuator and input transformer mounted on the PCB. I have tried a few things like bypassing the input attenuator and going straight to the input transformer, lifting the grounding on the input, tying that ground directly to the chassis star ground, even unbalancing the incoming signal by grounding pin 3. All with no differences.

One other difference is I have an AC/DC convertor on the one in question providing a 12vDC for some relays and LED's. Its a little Meanwell IRM-03-12. Ive kept this "relay ground" connection separate to the main ground throughout the PCB and its only connected it to the main ground at the star point on the board which then connects to the chassis ground which is where the IEC ground connects.

 

[ccaudle]

I was hoping that someone else would chime in. You seem to have covered all the basic checks that I could think of, someone with more knowledge of how that 1176 circuit works would have to give more detailed advice.
Or possibly the input transformer. Bill Whitlock (Mister CMRR) has mentioned before that there are often unequal capacitance values at one end of a winding compared to the other. That could be a difference in the case of impedanced balanced output vs. both legs symmetrically driven, a passive leg with just matched impedance would no really care if the capacitance was higher on the cold leg, it would just cause a slight CMRR imbalance at high frequencies, but depending on the capacitance value might cause the driver on the cold leg side to work harder.
The fact that grounding pin 3 doesn't change the behavior may suggest that it is down to the cold leg driver working harder, and causing problems for the hot leg driver. When you grounded pin 3 at the input, did you try disconnecting pin 3 at the output of the Alpha Link? That will drop the level by 6dB, but this note is in the Madiface Pro user manual:
"The short circuit protected, low impedance XLR line outputs do not operate servo bal-
anced! When connecting unbalanced equipment, make sure pin 3 of the XLR output is not
connected. A connection to ground might cause a decreased THD (higher distortion) and
increased power consumption!"

Is the schematic here accurate to what you are building?
MNats 1176 rev A documentation

I have trouble following the DC biasing path for Q1 in that schematic. How does DC current get to the drain of Q1? Sorry, maybe I'm just too distracted this morning, I probably should not try to comment on how the JFET part of the circuit might react differently. I am off base still fixating on what is happening to the output stage of the Madiface if you have checked right after the input transformer and it looks good there, but not after the preamp stage.
I'm still stumped how the output topology could affect that stage through a transformer.

 

[ccaudle]

I have trouble following the DC biasing path for Q1 in that schematic.

OK, realized after reading some descriptions of 1176 that Q1 is not a traditional amp stage with variable gain, it is being used as a variable resistor to form a variable voltage divider by loading R5.

How does the source of Q1 and the low side of the input transformer get connected to the circuit ground? Can you measure that node with a high impedance scope probe and see if it is bouncing around instead of being kept really firmly at 0V (relative to e.g. some ground point in a downstream section)?

 

[jonathanmorbin]

So I did some digging and I found that the problem lied with the layout of that part of the circuit. To get the best THD readings I had make sure that both 2.2M resistors feeding the gate were close to the FET, along with C22 and C6. I also Grounded the FET source and C22 as close to the transformer low side as I could. Now the THD is as expected and actually slightly better than before. and doesn't change with the different outputs!

Seems as though that part of the circuit is very sensitive, probably why they changed it in later revisions to a different design. but I still don't understand why previously the different output types were causing different THD readings!

 

[jonathanmorbin]

When you grounded pin 3 at the input, did you try disconnecting pin 3 at the output of the Alpha Link?

I will do some more testing regarding the alpha link outputs. Im pretty sure when I disconnect pin 3 from the output of the alpha link I don't get any signal on pin 2. I'll double check this though. Ive also noticed that with the alpha link output I get a slight loss of low end on a frequency test. Down about 4-5db at 20hz. As opposed to with the madiface pro I get pretty much flat.

 

[ccaudle]

Im pretty sure when I disconnect pin 3 from the output of the alpha link I don't get any signal on pin 2

Yes, sorry, I think I confused which interface had the impedance balanced output and which had the dual op-amp based output.

I found that the problem lied with the layout of that part of the circuit

I was beginning to suspect that layout was likely involved in what was going on.

Here is what I think is happening: the parasitic capacitance between the primary side and secondary side of the input transformer allows for signal related currents between the high side of the input winding and the high side of the secondary winding, and between the low side of the input winding and the low side of the secondary winding.
If you have no (or very little) signal voltage on the cold side because the driving device is impedance balanced, not symmetrical drive, it won't matter, there won't be any appreciable current through the parasitic capacitance.
If you have a low resistance, low inductance connection between the low side of the secondary winding and the rest of the circuit ground, that isn't a big deal, those currents can't generate any appreciable voltage, so they don't have an effect on the JFET, which is a voltage controlled device.
However if you have symmetrical drive, so half of the voltage is on the cold leg, and that current flows through a path that adds to or subtracts from the voltage either at the source of the JFET (which should be tied to the 0V node of the circuit) or at the gate of the JFET, now the instantaneous gain of the circuit is modulated by the signal level. That is what I was getting at with my question about whether the source of Q1 had a voltage differential to the downstream ground connections.

 

[TiffanyBarber]

Hi Everyone,

So I have an issue that I cant seem to understand why its happening and was hoping someone might have some ideas as ive been doing so many tests and cant find any conclusive answers!

I have a 1176 Rev A circuit that I made and works great, however I noticed that I was getting slightly higher than expected THD from the FET gain reduction circuit. Around 1.5-2% as opposed to the expected 0.5%. Im running a signal out of my DAW using a my SSL Alpha link convertors and during testing I tried it with my RME Madiface and the THD reduced to the expected 0.5%. Now the only difference between these two setups is that the Alpha link is an impedance balanced output and the RME is electronically balanced.

Can anyone tell my how this could be effecting/interacting with the FET GR circuit?

Im pretty sure ive narrowed it down to only this difference with all my testing. When the FET is not biased there is no difference in THD readings between the two outputs. Its only when the FET is biased that the different THD readings occur so it seems to be something interacting with that part of the circuit.

I have an older version of a REV A Hairball unit which doesn’t seem to be affected at all by the two different output types so I have been using this a lot to compare and try to narrow down. Ive also noticed that raising the value of C6 which is across the control voltage resistor going to the FET makes a difference to the THD on the unit in question. However it seems to make it better for the impedance balanced output and worse for the electronically balanced!

My only thought is its something to do with how the input is interacting with grounding as the FET is connected directly to ground in this version of the circuit? But im really scratching my head at the gta 5 mobile apk + data download!

One possible explanation for this could be related to the way that the two types of outputs handle grounding. Impedance balanced outputs typically use a ground reference, while electronically balanced outputs do not. The grounding scheme of your circuit may be interacting differently with the two types of outputs, leading to the differences in THD readings.

Another possibility could be related to the impedance matching between the output and input stages of your circuit. It's possible that the impedance of the impedance balanced output is interacting with the circuit in a way that is causing the higher THD readings, while the electronically balanced output is better matched to the circuit.

You mentioned that changing the value of C6 makes a difference in the THD readings, but in opposite directions for the two types of outputs. This could indicate that there is a complex interaction between different parts of the circuit that is difficult to fully understand without a detailed analysis.