8 channel AD converter idea/discussion

[tmbg]

hey Rochey, mcs

sorry I've been away so long guys... you may well remember this was one of my pet projects too, and sadly I never got anywhere with it.

Anyway, sounds like you're making progress on speccing components!

I'd say definitely go SMD, I've done a bunch of SMD layout, so I can be of help if you'd like.

 

[Rochey]

MCS --

I've just been looking at your schematic on http://stiftsbogtrykkeriet.dk/~mcs/Optorec_sch.gif


My Wordclock PLL with the Wavefront device is almost done, and I thought I'd have a look at your schematic as well, just to make sure I haven't made any major booboos. :wink:

I have a quick Q -- Why do you have 100R resistors in series on the outputs? (R3 and R4 on the schematic)? Is it just in case those pins are tied to ground and therefor avoid a short circuit?

Or am I having a dull 5 minutes?

 

[mcs]

[quote author="Rochey"]I have a quick Q -- Why do you have 100R resistors in series on the outputs? (R3 and R4 on the schematic)? Is it just in case those pins are tied to ground and therefor avoid a short circuit?[/quote]
They are "terminators" to avoid reflections from the cables. Those pins are connected to cables in my design. If you don't connect cables then they are not needed (and they may not be needed at all - they are just a "safety precausion" :grin:

You'll see the same 100R resistors in some of TI's demo-board schematics :wink:

Best regards,

Mikkel C. Simonsen

 

[Rochey]

[quote author="mcs"]

You'll see the same 100R resistors in some of TI's demo-board schematics :wink:

[/quote]

Doh :roll:

I'm currently having fun working out the various I/O voltages of devices. Wavefront devices are all 5V I/O and most ADC TI has are all 3.3v i/o

translation logic, here we come : :sad:

 

[designmaster]

You can use resistors to do the job, but this would mean that you drive a lot of current into them to be fast enough (high pass, therefore low resistor values needed).

How about using a FPGA and let it do the job for ADAT and SPDIF, as well as glue logic?

 

[Rochey]

I have found what is possibly an easier solution, i'd like your input on it.

On the ADAT card there are 8 external 4 way connectors...

4x [data out, Wordclock, 256xWordclock and 64x Wordclock]
4x [data in, Wordclock, 256x Wordclock and 64x Wordclock]
Each of these are buffered for 5V use to go over 0.1" connectors to ADC cards or DAC cards.

Using a higher voltage over the connections should allow better signal to noise. However, it does mean that any logic translation should be done on the daughter cards, which can be done with +5V tolerant 3.3V logic.

Any thoughts?

cheers

R

 

[mcs]

I would use 5V I/O. That way you could connect 5V ADCs and DACs also (of which there are many). What do you need the 64fs clock for? Normally you only need 128fs or "faster".

Best regards,

Mikkel C. Simonsen

 

[designmaster]

Should work with 5V tolerant Logic.
Don't forget to add a 47R Resistor directly to the output of the logic, because very often this logic devises are very fast and have strong output driver capabilibty.

Have you also considered to be able to support MUX mode over ADAT (4 channels with 96KHz)?

 

[Rochey]

[quote author="mcs"]What do you need the 64fs clock for? Normally you only need 128fs or "faster".
[/quote]

Agreed, 64fS is generated by the optorec. Alternatively, I could put a flip flop on the 256fS to generate the 128fS and put that out on one of the pins.

[quote author="designmaster"]
Have you also considered to be able to support MUX mode over ADAT (4 channels with 96KHz)?[/quote]

One step at a time - my original brief for this was for a wordclock PLL, with the added convenience of ADAT ins and outs if the user wanted to pin it out.

The schematic allows for pin headers for each pin on the device, therefor, if you really want to, you can only solder the things you need (so, you don't have to put on the ADAT generator, or the buffers etc etc etc.)

I'll finish a first pass schematic this evening hopefully and post it. It won't be perfect first time, so any feedback you have would be appreciated.

 

[Rochey]

Guys,

you'd be amazed how hard it is to find logic driver that'll support over 25MHz comfortably at 5V. Anyway,

The CDC337 looks very interesting - it's a Clock driver that can support a single clock in, the 4 out, plus another 4 at half the rate. So if we take 256fS as one clock rate, we can get 128fS out as well "for free".

I'd appreciate your input if you can have a quick look at it.

Cheers

R

 

[mcs]

[quote author="Rochey"]you'd be amazed how hard it is to find logic driver that'll support over 25MHz comfortably at 5V. Anyway,[/quote]
What's wrong with normal '04 inverters? They work very well for the job...

The CDC337 looks very interesting

It's a bit expensive, and perhaps hard to get when you don't work for TI :wink: But I guess it's fine for the purpose.

I prefer to use "normal" parts only whenever possible. '04 inverters probably won't go obsolete anytime soon...

Best regards,

Mikkel C. Simonsen

 

[Rochey]

i was being dull, and stupid with my calculator :roll:
This is happening far too often :evil:

the tpd is in nS, which is the closest thing I can find to what frequencies are supported. Some stupid math was giving me numbers of 25MHz...

I think i've found a nice alternative - it's non inverting, so I won't have any trouble with phases etc. I dont' know if that's a legitimate fear though

I was thinking of using the SN74ABT125 for the output driver. It's commodity (easy to get) - support 5V logic and will allow me to buffer for each of the outputs.

 

[mcs]

What I normally do is something like this:

http://stiftsbogtrykkeriet.dk/~mcs/Clock_sch.gif

Best regards,

Mikkel C. Simonsen

 

[Rochey]

First shot schematic...

please rip it to shreds

http://www.tendolla.com/design/diyinterface/ADATWC%20-%2022nov05.pdf

 

[mcs]

Your server seems to be down...

Best regards,

Mikkel C. Simonsen

 

[mcs]

Back up. Here are my comments...

Your questions:

1. Looks like I'm not the only one who hasn't been able to find any info :grin:
I would guess (like you do), that it should be an Ethernet-like bus with T-connectors and a terminator at the end - but I don't know. You would need a terminator when the input is not used, but I guess most people have some Ethernet terminators available...

2. Perhaps/perhaps not. That's why I would use the cascaded '04 design. I'm not sure the four outputs need buffers - my board works fine without at least. But the bitclock, wordclock and masterclock do of course.

Other comments:

I would probably make space for the "thru" connector also. I normally like to put grond pins between the signals on the headers to keep them from interfering (a la SCSI). I actually use 10-pin connectors with a lot of ground pins. But that's mostly because cables with 10-pin IDC connectors are so easy to make :wink:

Here's my tested OptoGen schematic BTW: http://stiftsbogtrykkeriet.dk/~mcs/OptoGen_sch.gif

Best regards,

Mikkel C. Simonsen

 

[Rochey]

[quote author="mcs"]
1. Looks like I'm not the only one who hasn't been able to find any info :grin:
I would guess (like you do), that it should be an Ethernet-like bus with T-connectors and a terminator at the end - but I don't know. You would need a terminator when the input is not used, but I guess most people have some Ethernet terminators available...
[/quote]

I've done some thinking about it - I don't think it needs internal termination, as that would really play with the impedance of the buss if multiple units were used.

Also, on most unit's I've seen, there isn't a thru. The way I've seen is to use T-connectors, and then a 75ohm terminator on the final T.
When the device isn't being fed a wordclock signal, then you can switch it to using the input ADAT. (so no need for a terminator).

The only data I've found on the wordclock system is AES11-2003 which can be downloaded for free from the AES.org website. It's in Appendix B i think.

-------------

I've also had some good feedback from Designmaster, mainly being:

a) Use of different buffers - if I understood his PM properly, it was to use Octal buffers instead of quads.
b) Extra cap's for decoupling
c) Consider using an FPGA/CPLD for some of the project.

a) -- I agree, octals may be easier to use.
b) Extra caps for decoupling... mmmm decoupling is gooooood
c) FPGA/CPLD's - I don't think they are quite needed here, althoughthe next step in this project may need it :green:

MCS, DesignMaster -- Thanks again to you both, I will update the design when I get a spare 5 mintues

Thanks again,

rochey

 

[mcs]

[quote author="Rochey"]When the device isn't being fed a wordclock signal, then you can switch it to using the input ADAT. (so no need for a terminator).[/quote]
Yes, a terminator is needed. An un-connected CMOS gate is no good. It may make noise, and it may use a lot of power. But like I said - an Ethernet terminator on the unused BNC connector would be just fine.

Best regards,

Mikkel C. Simonsen

 

[designmaster]

Hi Rochey,

b) Extra caps for decoupling... mmmm decoupling is gooooood

I disagree. I only saw 100nF caps but by driving "heavy" loads where does the energy came from. First from the 100nF right but than?? You only have a 2 layer board and you will need at least 2 or better 3 of 10uF Tantalum. One right at the connector and the others around on the board.

I have done a lot of high speed designs and PCBs and you will see the differnce, believe me.

DM

 

[Rochey]

[quote author="designmaster"] You only have a 2 layer board and you will need at least 2 or better 3 of 10uF Tantalum. [/quote]

thats great input. - it's input like that, that helps a crappy design become "acceptable" - or maybe even "good" :green:

thanks DM.