Andy Peters
Well-known member
[quote author="TobWen"][quote author="jdbakker"]I also said that the faster the logic family (more precisely: the faster the rise/fall times), the more noise it will generate. You want logic that is just fast enough (within the full operating rate, naturally), but no faster. I have not seen any evidence that LVC hits that spot.[/quote]
I've read this again:
Aren't good fast rise/fall times important for clocking-signals?[/quote]
Yes, but you don't want "too fast" because you'll have EMI problems as well as signal-integrity problems (ringing/overshoot leading to double-clocking and worse).
Also, a series termination resistor at the driver and matching the driver output impedance to the PCB trace goes a long way towards mitigating transmission-line effects.
"Flank-direction" ??? What is that?
-a
I've read this again:
Aren't good fast rise/fall times important for clocking-signals?[/quote]
Yes, but you don't want "too fast" because you'll have EMI problems as well as signal-integrity problems (ringing/overshoot leading to double-clocking and worse).
Also, a series termination resistor at the driver and matching the driver output impedance to the PCB trace goes a long way towards mitigating transmission-line effects.
A friend of mine also added:
When choosing full synchronisation, it might happen that meta-stability appears between SCKL and LRCK. The flank-direction of SCKL is important.
"Flank-direction" ??? What is that?
-a