A/D converter sample rate conversion side-effects?

[gentlevoice1]

Hello again,

Thanks for replying ...

@JohnRoberts: Thank you for clarifying John. This makes the THD & noise specifications more accessible to me and also something that I now can calculate from specs ;-)

@ricardo: Hmmm... I'm aware of what you write in terms of PCB layout, wiring etc. I don't consider making a superb ADC a "pic nic" but something that I am quite careful about doing, thus clarifying as much as possible beforehand (and underways). To that end I have to say that I prefer to get factual information rather than opinion as this makes it more feasible for me to make my own decisions and assessments.

Although I - admittedly! - am not a technical expert I have worked about 20 years with audio on more levels - as a high end audio sales person, extensive DIY (often doing things differently), and having a quite close connection with a high-end audio designer company (cds, loudspeakers & amplifiers) for many years. As I said I am not a technical expert but I do have quite some experience with what sounds good - to my ears - and why this may be so, and also in what direction my preferences go.

And then to revert to the ADC: Guido tent of tent audio has e.g. posted a paper on his webpages about layout of a DAC and there's also been some other posts on the net about these challenges (e.g. on diyaudio).

Best regards,

Jesper

 

[Twenty Log]

The most important factor isn't what Golden Pinnae components you use or even the AD/DA chips.  It's the PCB layout, construction & wiring.  Even the true gurus will need at least one prototype PCB iteration if done from scratch.

Maybe 2 or three design iterations at least; multi-layer PCB preferred = $$$$....  That and a Signal Integrity Simulator, with *good* IBIS models (used to not be so common to have actually good models way back when with experimental/ASIC or moderately new chips), will get you within 20% to keep ringing down on clock lines for the initial PCB design spin....  One can also spend $1500+ for a Wenzel clock crystal that would surpass the phase noise spec ("better jitter spec") even of the finest $6000 Swiss-made clocks only to have internal clock pin logic threshold cross over variability/noise introduce jitter internally to the A/D chip (which may bring up the noise floor or side lobes depending on jitter shape/periodicity)...  Just sayin....

Watch for idle tones in industrial non-audio chips...  May not be an issue for the particular chip you mention (haven't looked at the data sheet)....  Analog noise can help with idle tones but sort of defeats the point...

 

[abbey road d enfer]

In addition to what ricardo says, you have to consider your complete system, not only the separate elements.
Are you gonna run your A/D on its internal clock always?
You may have to operate with WC sync, which would introduce a PLL in the clocking system; then all your efforts at having a super-stable super-clean clock would be useless.

 

[gentlevoice1]

@abbey road d enfer:

Are you gonna run your A/D on its internal clock always?

Thank you also for commenting ... & yes, I will only be running it on the internal clock.

@Twenty Log: Thank you for commenting but I won't be going into such equipment that you mention ... but maybe I can ask you to take a look at the ADS1675's datasheet to see if there's idle tones? I've attached the datasheet to reply #6 in this thread ...

Best regards,

Jesper