[quote author="Samuel Groner"]Hm, if I simulate things with your compensation values and 2N4401/2N4403s, I get a phase margin of 10° at 1 MHz and about 25° at 10 MHz (unity gain crossover point). Transient simulation is not stable, and my feeling is that real world will give similar results.
Are you really sure that this design is worth breadboarding without the intention to build a HF generator? :? (Not that I would have time for it.)
I tried different compensation schemos, but none provides the stability I usually aim for.
I also bypassed the bases of the CB Q's to the rails with 1u each.
Stupid one: which are common base here? Q1-Q4?
Samuel[/quote]
I can't account for your differing results without more details, but I see closed loop a pretty decent phase margin with the closed loop circuit as described. Note that the ~60MHz GBW (really the unity-gain freq, not the -3dB open loop freq) was examined open loop, with the offset voltage tweaked with a generator---something that a simulator can do but would be impractical on the bench. It wasn't a pretty phase response but steered away from the rocks, and was more or less validated by the closed-loop behavior.
I didn't and don't propose that one spend time breadboarding---there are more satisfying designs to do that with. Also, as I said, the layout will be critical when there is still as much gain at high frequencies as the sim predicts for me, which means parts of the board at least should probably be SMD. However, I think the sim results I stated are not too far from reality. But the drawbacks include a lumpy phase margin and associated Bode plot which translate to a worse-than-single-pole-dominated transient response, hence slower settling time. Whether or not that is an audible thing or not is controversial. I merely wanted to see how far the design as shown could be pushed.
The common-base stages I'm referring to in the original schematic are Q5 through Q8.
After some days away from electronics altogether I did a bit of more analytic work last night, after crafting an improved second stage with CFP's and lower C/higher BW transistors, and a cascode CB stage. This works well but does restrict output swing some. I looked at the open loop response and used that as a guide to what would be required in the first stage to ensure single-pole rolloff overall. The results are pessimistic w.r.t. noise, unless one resorts to L's in the emitters which I wanted to avoid at least initially.
Anyway, a very decent settling of about 65ns to ~99.9% of a step could be achieved, with a slew rate of about 265V/us, with a gain of two and feedback and feedback divider R's of 200 ohms each. But the transconductance of the first stages had to be substantially reduced, with emitter ballasting of about 480 ohms for each input device, which means the equivalent input noise would be no better than 2.8nV/root Hz, worsened further by thermal noise in the 1k load R's as well. I preserved the compensation topology but the major networks across the 1k load R's get pretty brutal at 14.4n in series with 110 ohms. There were a few other tweaky comp networks needed to fine-tune things.
So---again an interesting exercise, but there are better ways.
