CMOS logic fanout

[audiox]

As far as I know there is no limit (in practice) how many CMOS logic inputs you can drive with one CMOS logic output. Or the first thing that starts to limit is the input or pcb trace capacitance. I guess that is why in datasheets fanout is given for CMOS>TTL situation but not for CMOS>CMOS.

Now I am in a situation that I have to drive 36 (yes 36!) 74HCT inputs with only one 74HCT inverter (no possibility to parellel the drivers). Is there something that I should consider except the capacitance? The circuit is intended to work up to 25 MHz.

 

[rlaury]

If all of the HCT's are close together, say within 10" 12" it shouldn't be a problem.
If they are spread across the width of a console 6', I would at least want a 2N2222
driver.

Hope this helps


RonL

 

[JohnRoberts]

I haven't done a lot of work with modern CMOS but I have encountered problems with picking up extra clocks when I was trying to latch some serial data due to poor rise time edges. I was trying to do a logic level translation between 3.3V and 5V using open drain and a pull up resistor, but it passed through the logic threshold slowly enough to cause errors. I suspect the edge was only an issue on the clock line and not for simple data lines that have a time window to set up. 

So it will depend on the application how sensitive it is and whether it can even switch that many loads at 25 MHz. With CMOS it also depends somewhat on the rail voltage.. more voltage gives CMOS better drive capability.

JR

 

[jdbakker]

Now I am in a situation that I have to drive 36 (yes 36!) 74HCT inputs with only one 74HCT inverter (no possibility to parellel the drivers).

Doable...

The circuit is intended to work up to 25 MHz.

...but that's pushing it.

You don't say whether you have a 25MHz clock that you have to ferry around, or whether the system can have 25 million transitions per second. I'm assuming the latter, as that's easier. This gives you 40ns for all level transitions. Typical Cin for HCT is 3pf, call it 5 with trace capacitance, makes 180pF total. Say we want to swing 2V, and that the driver can maintain full output current regardless of output voltage. This means the driver would need to supply

I=C*dV/dt=180pF*2V/40ns = 9mA.

For a simple HCT gate that's probably outside its comfort zone. It might do the job, if supply and ambient temperature are just right. I would not bank on it. Get a hi-current bus driver chip, find a way to distribute the line over more drivers, find a way to reduce the number of receivers, reduce your switching speed or learn to live with a system that's marginal, intermittent or just plain dead.

Did some more reading: the 74HCT245, which is optimized for heavy lifting, has a specced transition time of 16ns typ / 40ns max for a 150pF load at room temperature. Over the full temp range and at low supply (4.5V) that figure increases to 53ns. I'm afraid you'll need to reconsider your plan.

JDB.

PS: You asked about other issues. For HCMOS-type transition rates on lightly loaded lines everything longer than ~30cm needs to be treated as a transmission line. Having lots of (evenly distributed!) capacitance actually helps here, as it reduces edge rates.

 

[Svart]

A couple of fets configured for a high/low side driver should do the trick or just get one of those nifty fet gate drivers and use it.  It should slew those CMOS gates pretty readily.

Although this is fairly low speed, you could have reflections from long traces which could falsely trigger other CMOS parts or other such problems.  As JDB says, treat these like transmission lines.  Once you do that you'll see that you'll need series resistors as well as termination resistors which will also cut your drive ability way down too. 

 

[audiox]

Jdbakker, excellent answer again (and thanks to other participants too). I have some new ideas but I do some calculations first.