Comparison of JFETs for mic applications

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Fair, but we’re only talking about a total of around 1%-2% THD before the improvement, which is barely audible.
If you say so; not everybody agrees.
If we were going from 10% to 1% the exercise would make sense.
The way NFB works, it is more than likely that at a level that results in 10% THD without NFB, THD with NFB drops down to less than 1%.
Looking at V10's graph, 10% THD happens at about 0.6Vrms, and NFB would drop it down to less than 1%.
Your concern that noise would become an issue if the gain is reduced too much is valid only for SPL levels that result in very low THD, whether or not with NFB.
Very low intrinsic noie microphones are the subject of a very different optimization, which often starts with teh capsule.
 
After simulations comparing U87 ORS with stock values of C6/C5 - 220pF/33nF with U87 (same values for capacitors) and U87A/U87AI schematics (C6/C5 - 160pF/47nF) my take right now is following (THD not taken into account):

U87 ORS frequency response and gain is similar to U87A/U87AI schematics and not as I was expecting the U87 'classic'. Maybe someone could confirm or refute it :).

If I add the feedback capacitor of 5pF in U87 ORS (C3 in U87 schematics), both the frequency response and gain is similar to simulation of U87 classic schematics.

With that I mean is the frequency responses seems to be quite different between U87 and U87A/U87AI and trying to change C6/C5 in U87 ORS to get similar responses as U87 was not easy. It was much simpler to just add the C3.
 
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Looking at V10's graph, 10% THD happens at about 0.6Vrms, and NFB would drop it down to less than 1%.
...when it's biased for 100mV. That's why I suggested biasing for closer to 1V. As @kingkorg has found, loud sources can produce transients as high as multiple volts. If you want headroom, bias it for headroom.


U87 ORS frequency response and gain is similar to U87A/U87AI schematics and not as I was expecting the U87 'classic'. Maybe someone could confirm or refute it :).
Yes, I made the ORS circuit as a simplified version of the U87, and since the U87A circuit is "simpler" (i.e., no C1, C3, or R6, etc.), the ORS circuit will be closer to the U87A circuit.
 
...when it's biased for 100mV. That's why I suggested biasing for closer to 1V. As @kingkorg has found, loud sources can produce transients as high as multiple volts. If you want headroom, bias it for headroom.
If you looked carefully, you would see that optimum bias for 100mV is not too different than optimum bias for 1V. This is electronics 101.
 
Just to add to the confusion... this is i presume for 1K signal, THD will vary greatly throughout the spectrum, the transformer will crap out much sooner at LF, so for 1% thd at 1K you will probably see much higher % at 50hz. Especially with these t14 style transformers. Then lower above 10k because of the increased negative feedback.

Using sinewave for THD is legit, but also somewhat deceiving. As soon as i started sweeping and listening dualtone, or even more complex signals i realized how audible, random, and unpredictable saturation can be even at crazy low levels.

I'm not getting any smarter when it comes to THD.
 
I hope it's becoming clear how many variables are at play here: start with FET type, bias current, C4 or lack of it. Then there's source capacitance and output load, after that there's C12/C13/R14/R15 in the feedback network.

For each circuit combination we want to know gain vs frequency, and THD against both frequency and signal level. THD is itself a proxy for more general nonlinearity, which (by definition) can't be captured just with fixed sine waves. (Edit: then there's noise to worry about).

So yes, the full picture is very much more multidimensional than what's being presented here; I'm completely aware of all the things I haven't (yet) investigated.
 
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If you looked carefully, you would see that optimum bias for 100mV is not too different than optimum bias for 1V.
That was certainly my impression, but can it be backed up with hard data? We need to know how THD varies with both bias current and input signal level.

Test conditions: J113 FET, C4 = 10pF, Rload = 47K, C12/C13/R14/R15 not fitted. 1KHz sine wave in. Figures are THD as reported by REW.

The individual THD measurements for a variety of input levels and bias currents are as follows. I've converted THD % figures to dB as they span a wide range (0.057% - 2.5%).

Bias (mA)44mV70mV100mV140mV220mV320mV440mV
0.2
-55.9​
-52.0​
-48.9​
-45.8​
-41.6​
-37.9​
-33.4​
0.25
-60.0​
-55.4​
-52.8​
-49.6​
-45.4​
-41.9​
-38.1​
0.3
-62.9​
-58.4​
-55.9​
-52.8​
-48.6​
-45.2​
-41.7​
0.35
-64.9​
-60.8​
-57.7​
-54.9​
-50.8​
-47.5​
-44.3​
0.4
-64.9​
-60.7​
-57.7​
-54.9​
-50.8​
-47.7​
-44.4​
0.45
-61.1​
-57.1​
-54.0​
-51.1​
-46.9​
-43.9​
-40.5​
0.5
-54.0​
-49.6​
-46.7​
-43.7​
-39.5​
-36.0​
-32.0​

If we plot them, it looks like this:

THD vs bias vs level.png

As is now plain, the optimum bias point (the lowest point on each curve) is the same, regardless of signal level, roughly 0.38mA. Not only that, but the shape of each curve is the same, meaning that it's no easier or harder to find this bias point with higher or lower voltages.
 
As is now plain, the optimum bias point (the lowest point on each curve) is the same, regardless of signal level, roughly 0.38mA. Not only that, but the shape of each curve is the same, meaning that it's no easier or harder to find this bias point with higher or lower voltages.
Thank you for backing up with hard facts my assertion, that was based on yeras and years of observation and reading.
 
Hi people... a very interesting discussion... and valuable for some not unsimilar work that I have been doing that was started by a local company - now defunct.
As a result of their demise I happen to have "acquired" a large number of (genuine) TOSHIBA JFETs. Which include the following. If these are helpful for anyone please PM me. Cheers
2SJ103-BL
2SJ104-V
2SJ148
2SK117-BL
2SK117-GR
2SK246-BL
2SK30ATM-GR
2SK30ATM-Y
2SK369-BL
2SK369-V
2SK373-GR
2SK709-V
 
The minimal variation in noise between devices in this application is a real surprise to me.
Thanks. It was to me, too - when I started I expected that FET choice was the key to everything. There is several dB difference between the best and the worst, but only in the right circuit. For the most common circuits, resistor thermal noise drowns out most of the FET's contributions.

I can't promise that these measurements are all that accurate in an absolute sense, but I hope that trying a lot of different things in the same test environment will give a good picture of relative performance.
 
Thanks. It was to me, too - when I started I expected that FET choice was the key to everything. There is several dB difference between the best and the worst, but only in the right circuit. For the most common circuits, resistor thermal noise drowns out most of the FET's contributions.
It may be interesting to evaluate noise vs. Vgd voltage. A significant part of the noise comes from the current circulating in the reverse junction.
 
Yes, that's perhaps best tested with the 'MicUlli' circuit (post #38) where Vgd can be set with a single resistor. More things to add to the list...
 

ORS87 with different FETs​

Here are some measurements with a variety of (through-hole) FETs. As in earlier posts, these were sourced as follows:
  • J113: OnSemi, CPC (Farnell)
  • 2N3819: bought in 1990's, probably from Maplin or Farnell, Fairchild marking
  • BF256B: OnSemi, CPC (Farnell)
  • J305: InterFET, Mouser
  • 2SK170: bought > 5 years ago, small UK supplier, can't remember
  • 2SK117: eBay, Chinese seller
  • 2SK30A: eBay, Chinese seller
Test conditions: C4 = 10pF, Rload = 47K, C12/C13/R14/R15 not fitted, 1KHz 100mV sine wave in. Measurements from REW.

Gain vs bias current​


ORS87 FETs gain.png

THD vs bias current​

ORS87 FETs bias.png

Summary table​

Includes the gate-source (Vgs), and the calculated value of the R7 trimmer.

J1132N3819BF256BJ3052SK1702SK1172SK30A2N3819 (SGD)
Id (mA)
0.37​
0.41​
0.43​
0.40​
0.36​
0.36​
0.45​
0.40​
Vd (V)
12.7​
10.5​
9.2​
10.8​
13.3​
13.0​
7.9​
10.7​
Vgs (V)
-1.64​
-3.32​
-2.10​
-1.70​
-0.63​
-0.91​
-1.49​
-3.33​
R7 (Kohm)
4.47​
8.19​
4.92​
4.26​
1.77​
2.51​
3.29​
8.25​
Gain
4.81​
4.61​
4.72​
4.71​
3.79​
4.64​
4.3​
4.55​
THD (%, 100mV in)
0.12​
0.17​
0.15​
0.14​
0.07​
0.078​
0.17​
0.17​

Is the 2N3819 reversible?​

The Internet (and various datasheets) can't agree on whether pin 1 on the 2N3819 is source or drain (and pin 3 is, respectively, drain or source). I have been using pin 1 = drain ("DGS", when looking at the flat side of the package) for most measurements, as per the Fairchild datasheet, but thought I'd try with it reversed ("SGD"). Results are in the final column above.

Basically, there's no meaningful difference, within the repeatability of the measurement setup. The gain difference (0.1dB) might be some change in drain-gate capacitance, but unlikely to make any meaningful difference to circuit performance, and almost certainly smaller that the difference between individual FETs.
 

ORS87 with different FETs​

Here are some measurements with a variety of (through-hole) FETs. As in earlier posts, these were sourced as follows:
  • J113: OnSemi, CPC (Farnell)
  • 2N3819: bought in 1990's, probably from Maplin or Farnell, Fairchild marking
  • BF256B: OnSemi, CPC (Farnell)
  • J305: InterFET, Mouser
  • 2SK170: bought > 5 years ago, small UK supplier, can't remember
  • 2SK117: eBay, Chinese seller
  • 2SK30A: eBay, Chinese seller
Test conditions: C4 = 10pF, Rload = 47K, C12/C13/R14/R15 not fitted, 1KHz 100mV sine wave in. Measurements from REW.

Gain vs bias current​


View attachment 135978

THD vs bias current​

View attachment 135979

Summary table​

Includes the gate-source (Vgs), and the calculated value of the R7 trimmer.

J1132N3819BF256BJ3052SK1702SK1172SK30A2N3819 (SGD)
Id (mA)
0.37​
0.41​
0.43​
0.40​
0.36​
0.36​
0.45​
0.40​
Vd (V)
12.7​
10.5​
9.2​
10.8​
13.3​
13.0​
7.9​
10.7​
Vgs (V)
-1.64​
-3.32​
-2.10​
-1.70​
-0.63​
-0.91​
-1.49​
-3.33​
R7 (Kohm)
4.47​
8.19​
4.92​
4.26​
1.77​
2.51​
3.29​
8.25​
Gain
4.81​
4.61​
4.72​
4.71​
3.79​
4.64​
4.3​
4.55​
THD (%, 100mV in)
0.12​
0.17​
0.15​
0.14​
0.07​
0.078​
0.17​
0.17​

Is the 2N3819 reversible?​

The Internet (and various datasheets) can't agree on whether pin 1 on the 2N3819 is source or drain (and pin 3 is, respectively, drain or source). I have been using pin 1 = drain ("DGS", when looking at the flat side of the package) for most measurements, as per the Fairchild datasheet, but thought I'd try with it reversed ("SGD"). Results are in the final column above.

Basically, there's no meaningful difference, within the repeatability of the measurement setup. The gain difference (0.1dB) might be some change in drain-gate capacitance, but unlikely to make any meaningful difference to circuit performance, and almost certainly smaller that the difference between individual FETs.
Have you checked what de-emphasis curve looks like with different fets? In my experience depending on bias and gain of the fet the curve shape varies widely.
 

Effect of feedback capacitor​

Here's your weekly dose of data, this time changing the C4 (drain-gate) capacitor.

Measurements are done with 3 FETs: J113, 2N3819, and 2SK117, and with 3 C4 options: 10pF (from previous posts), 5pF, and none.

As before, Rload = 47K, C12/C13/R14/R15 not fitted, test signal is 1KHz 100mV sine wave in via 68pF source capacitor.

Gain​

Gain vs C4.png

THD​

(Note vertical axis is logarithmic, due to wide range of values)
THD vs C4.png

For each FET, the shape of the curve (THD vs bias current) is the same, which suggests you don't need to adjust the bias if you change the C4 value.

In numbers​

Here are the numbers (in normal units, not dB), as measured at Id giving the lowest THD.

ValueJ1132SK1172N3819
Id for measurement (mA)0.40.350.4
Gain, 10pF4.794.654.62
Gain, 5pF7.437.137.05
Gain, 0pF17.716.415.8
THD (%), 10pF0.130.0790.17
THD (%), 5pF0.30.170.37
THD (%), 0pF1.660.91.58
 
As U87 ORS schematics is a mix (and simplification) of U87 classic (vintage) and U87AI and I don't see the NFB capacitor in U87AI schematic version I have been looking at, I wonder about the THD of U87AI. Is the THD in U87AI any worse than U87 classic? If not, what keeps THD low in U87AI compared to U87 ORS?
 
Interesting question. The U87Ai schematic at https://groupdiy.com/threads/neumann.44805/post-561146 certainly doesn't show one. Does anyone have a picture of the circuit board? Perhaps there are a few pF parasitic capacitance somewhere?

I don't think the C12/C13/R14/R15 network would add any useful NFB over most of the frequency range. At 1KHz the AC signal at the backplate is ~40dB down on the drain voltage, according to LTSpice.
 
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