Miller C occurs only when the drain has an inverted version of the signal at the gate - so it doesn't apply to followers, for example. Miller effect will multiply the Crss (drain-to-gate) C by the actual in-circuit voltage gain. So, if you use it "grounded source" (it's what the last s in Crss signifies, BTW), and choose a drain load resistor that gives the stage a gain of 10, then the input capacitance seen at the gate will appear to be 10 times the Crss figure. This is in addition to the normal Ciss (gate-to-drain) capacitance. So, in the gain of 10 circuit, the input capacitance would be (10 x 0.5 pF) + 7.5 pF = 17.5 pF ... using the "typical" numbers from the data sheet.

Of course, stage gain is transconductance (Gfs) x R load - in this case 2.0 milli-mhos x 5 kΩ = 10 ... and 50 kΩ would give a gain of 100, etc. ... again using the typical Gfs figure from the data sheet.