Spencerleehorton said:
Now I'm confused, your saying one minute that the chip is a replacement for the sad1024, now your saying don't bother trying to implement it in the 16 pin?
They are not that same chips.... I've already said this the SAD1024 has two separate 512 stage ASRs inside. The MN3207 has one 1024 ASR inside. It will only be functionally equivalent for that specific application because the MXR flanger ran the two halves of the SAD1024 in series.
I don't know anything about this sort of thing but already I'm getting very confusing information, from the schematics I've seen which use the 8pin chips (3007,3207) it's seem they add a transistor on the output and a cap is reduced in pf a little.
No the outputs of the BBD delay are already MOS source followers inside the chip. Some cheap designs may add a transistor configured as a LPF, there can be substantial clock frequency component, if you don't trim for the output buffer Vgs. You probably won't follow this but BBD ASR only pass one sample of signal per complete clock cycle (one half period up one half period down). This sample is only valid for 1/2 of the clock period. To present a smoother output waveform the BBD has a 1/2 stage delay built in to feed a second buffer, so the one output sample per clock gets presented by one mosfet follower for one half clock, then the other mosfet follower the other half clock period. Since these mosfets will not have identical Vgs, there will be a small clock waveform superimposed on the audio output. Premium designs add a trimpot between these two source outputs to trim out that DC clock component. Cheaper designs just ignore and hope to filter it out with the anti-imaging filters typically used to reconstruct the output from time-sampled wave streams. (did you follow that?)
Is it just these changes you are referring to, or is there some other changes?
So far I've seen a lot of schematics and talk about this but no definitive results of these changes, as most of this has ended up in schematics being drawn up and when tested they don't work.
Look at the data sheet for the part you plan to use (3207). It will provide the information you ask, like range of operating voltage it will work over, ballpark input bias.
The audio signal being passed internally will need to be biased at a DC voltage some fraction of the total supply voltage that delivers maximum clean signal. In professional designs we used a trim pot there and looked for symmetrical clipping on the output when optimally adjusted. BTW this optimal bias voltage can change with clock frequency so maybe check at both clock frequency extremes to pick the best compromise. Letting the HF clock end be a little dirty will make for richer flanging but the 1024 long line will not be as short as 512 used in micro flanger or studio boxes so less complete cancellation at short delay end.
The prototype BBDs I got to work with in the early '70s not only had a bias shift with clock frequency, but would cause a DC output level shift with clock frequency that could be problematic for fast changing clock applications. For slow changing clocks (like a flanger should be) this changing DC will be LF and below the passband LF cut off.
Cheap guitar pedals will not likely trim clock noise or trim input bias voltage, but you will at least need to bias up the different maker BBD chip to a different nominal input bias. The odds of the two chip processes from different manufacturers decades apart being the same are extremely unlikely (do you feel lucky?).
The clock commonly used for these was a CMOS D-type flip-flop configured as a divide by 2 so 50% duty cycle was guaranteed. I suspect the same clock as used for the SAD will work for MN part. Note the clock chip needs to be connected to the same +V as the BBD. A higher voltage clock than the BBD is connected to could unintentionally bias on some internal parasitic junctions and damage the BBD.
Read the data sheets, maybe dig up some modern clone schematic already using the MN parts for some other ideas to copy.
JR