New Mic Pre Design

[sbeach]

Hi,
Here's a schematic for a mic preamp design I've been working on. It's not been built yet but I will try to put one "test" channel together on a breadboard to experiment & troubleshoot.

http://twin-x.com/groupdiy/displayimage.php?pid=200&fullsize=1

It has the Burr-Brown INA103 instrumentation opamp as the 1st gain stage (I have several free samples). This opamp is used as a sort of input transformer substitute which has gain adjustable from 0 to +30 db in 5 db steps. This approach will save $$ compared to an expensive input transformer & hopefully will be quite transparent sound-wise. I've heard that the Grace 801 preamp uses this same instrumentation amp so I expect it to be somewhat like the Grace's "straight wire with gain". Also, please assume that before the input there will be suitable 48v phantom power in place with 47 uF blocking caps. I purposely left that out to save space on this schematic.
The second stage is a simple class-A JFET amplifier with a JFET follower. This amp's drain voltage is set at 2/3 the supply voltage & is mean't to mimick a triode tube preamp stage - not unlike that found in a Fender guitar amp. The "boost / color" switch engages a source bypass cap which optionally should reduce all but 2nd order harmonic distortion and boost the stage's gain by 6 db. Hopefully, when driven hard, it should provide a smooth & sonorous tonal color. The simple source follower JFET gets it's DC blocked on the output to go to a 10k audio pot (front panel) before the final third amplification stage.

This third gain stage is structured so that it maximizes the available supply voltage & places the audio signal at near 1/2 the DC supply - much like the input to Scott Hampton's Hamptone design from his now-famous TapeOp article. This stage too has a source bypass cap that can be switched in or out. This gain stage meets the outside world through a buffer that can put out some serious current if need be. The output is left unbalanced without a transformer as this has worked very well for me in the past.

Yes, I know a lot of folks don't like coupling caps in the audio chain but my experience is that, if correctly biased & bypassed with polypropylene caps, coupling caps are nearly inaudible in most cases. However, I do think the fewer the better.

I expect this preamp to be able to suitably provide clear, clean gain for a classical recording approach. Optionally, by increasing the 1st stage gain & trimming back the output of the second gain stage with the 10k pot, it should be able to add a smooth to dirty & colorful tonal component to the signal. I could be wrong :sad: . It's happened before.

I have tried to choose the individual JFETS in each stage for appropriate input headroom & desired gain. My plan is to adjust the drain trimpots for each JFET to the chosen DC voltage & then replace the trimmers with regular resistors.

OK, now please tell me where I'm going wrong! Plus a few questions for you all ...
On the final stage would it be better to use a simpler, single-supply output buffer (maybe a single NPN transistor ie BD139) and lose the coupling caps between the gain JFET & buffer? Is the single 24 v supply feeding the two final stages capable of enough headroom for normal use? Are there resistor or capacitor values that should be re-thought? Is the whole aproach to gain structure balanced & flexible enough?

Please peruse the schematic & tell me your thoughts about this project. I truly welcome all of your opinions and pointers. Thanks,

Skip Beach

 

[Kev]

I take it that you want high gain and don't want to use the INA213/2015/17 for full gain
so
you have a INA103 for the imp conversion and the cmr then through a couple of gain stages for a cool sound and drive
for a total of 70+ gain

" Grace 801 preamp uses this same instrumentation amp "
right at the front door?
if you know this, then fine for you to try too

looks like you want a clean and then at the flick of a switch ... colour
but you won't have lots of gain ... clean

I thought for " clear, clean gain for a classical recording " you may need the high gain

good idea but I think I'd make a colour mic-pre AND a clean mic-pre
clean perhaps INA103+IA103+JLMHybrid
just a thought

 

[Samuel Groner]

Just two quick thoughts:
* the two 100 ohm resistors biasing the four-diode string in the output stage look wrong--I guess you should try something around 5k ohm.
* be aware that if you distribute gain amongst several stages you will loose some of the excellent noise performance of the INA103. For a condenser it doesn't hurt but for a ribbon it might.

Samuel

 

[sbeach]

Hello Again,

Kev & Samuel - thank you for your helpful & insightful comments! I have a response or two & have changed & redrawn the schematic just a bit.

http://www.twin-x.com/groupdiy/displayimage.php?pid=201&fullsize=1

Kev - The INA103 instrumentation amp is very much like the INA217 and/or the 2017 in that it is a full-fledged mic pre in itself. It suffers from a less-than-perfect output stage, however. That's why it is loaded so lightly with the 10 Meg resistor. It is a very low-noise device as Samuel said & has great CMRR, etc.

The whole idea of this preamp design is flexibility. I hoped to come up with a design that could be very clean-sounding in one setting, but with a few switch & pot adjustments, could add a lot of it's own character too. For classical music recording & a clean kind of sound, the approach is to use up to 30 or 40 db of squeaky clean gain from the INA103 & then have additional low-noise gain added by the other two class-A stages - with the "color / boost" switches in the "off" position & the 3rd stage volume pot up near 100%. These stages add another 26 db of "relatively" clean gain for a possible total of +66 db. Then, for a more "colorful" sound with louder sources such as drums, piano, close vocals, etc., one could trim back the 3rd stage volume control to 30 to 50%, switch in one or both of the source bypass caps (+12db for both), & crank in the remaining necessary gain with the INA103 amp.

After reading yours & Samuel's comments, I have updated the schematic. Two more switch positions were added on the INA103 for up to +40 db for that stage. Also the 2nd stage JFET amp has been changed to a KSK30 - lower noise than the original 2SK246. Additionally, the 3rd stage buffer has been simplified to just a single MJE800 darlington. This change allows me to get rid of the coupling cap between that stage's gain amp & the output buffer but it should still have plenty of current capability. I think this is a better design now & I thank you for your observations.

Skip

 

[PRR]

> plan is to adjust the drain trimpots

Trim the cathode resistors, not the plate resistors!!! (Whichever you call them in JFETs.) You know you want about so-much plate voltage and plate current, so you know your plate resistor already. 10K seems fine. Your problem is that JFET cathodes (gate-source junctions) vary 3:1 or more in voltage and current. Fiddle that resistor to make the plate sit at 13V or 15V.

OR--- since you need a large negative voltage anyway (for the chip), run a large source resistor to V-. About 22K. Now the plate voltage will come out right, on ALL devices, even if the FET's turn-on voltage varies several volts from device to device. If one FET's Vth is 1V, and another's is 3V, 300% change, the voltage across the 22K varies from 25V to 27V, the FET current varies less than 10%.

Yes, the gain will drop to less than unity, which is stupid. Add an R-C bypass network to ground. If you think 787 ohms gives a good clean sound, use 820 ohms in series with 100uFd. When you want funk, short the resistor to max the FET's gain and nonlinearity.

I have no idea why you show variable resistors under the cathode followers. You know the voltage, you have a current target, the resistor value can be known. It won't be critical. All that trimpot can do is accidentally go to zero, try to pull 13V/0= infinite current, and smoke something.

That last stage with 10K cathode resistor will drive 22K inputs fairly well, but will suck bad with any true 600 ohm load you may meet. This may not be an issue in the Modern Studio. If it is, a good operating point (for BJT) is the DC resistor about equal to the AC load, and the emitter sitting about 2/3rd the way up the power supply. With emitter at +16V, and 560 ohm emitter resistor, you could drive 600 ohm loads to almost +/-7Vpk or 5V RMS.

If the previous stage can swing that far... in this case, it may be making over 10% THD at 7V swing. You can fiddle the interstage voltage down, to give the driver more up-swing, at the cost of reducing down-swing on the output stage. Half-way is often an unbeatable guess.

What is the voltage drop across the 10 ohm resistors in the power rail? What if they were 100 ohms, any real difference? What does 100 ohms do for supply crap rejection? Or cost of rail caps (220uFd looks rather oversize for an amp working at 10K impedances)?

Why are there three different JFET part numbers? Won't this drive your production and maintenance staff crazy, increase costs through lower-quantity no-discounts? If you just build one or two channels, isn't it a dollar easier to buy a 10-pack of one type than order 2 and 2 and 2 and keep them straight?

The 10Meg on the INA output is probably pointless.

 

[Kev]

thanks PRR for the details
I can't add much more to all that

except perhaps to point out that, when I used the 2017 and it's friends I did use an LM833 for the buffer and a little gain .. but not as much as you are looking at
and
I used a SSM2142 for drive ... it to added a little gain ... again you are looking at much more

So I do get where you are coming from and agree that these all in one chips do benefit from a good dimplementation of the idea.

I tend to use 33 ohm and 10uf tants as chip power bypass ... Neve IC was in the order of 47uf.
220uf is much larger perhaps a little over the top
either way .. keep it close to the power pins of the IC.

I'm not adding much to the stuff above ...

yeah 10 meg ???

It suffers from a less-than-perfect output stage, ...

I think you have over shot again
the IC can handle lower than 10meg for sure
in fact a specified load may turn out to be an advantage.
what does the application note recommend as a load ?

 

[Gus]

You should not need the 2nd SF fet.

Like PRR posted set your drain Rs. Knowing that scale the vol pot too the Drain R and advailble current or just make it much bigger.
The next stage is a fet and it will have low noise up to megs of input R. Also like PRR posted you have -24VDC
Also with higher value Rs you can use film caps.


Drain trimpots? sbeach do you build effects and read at Aron's and other sites?

 

[sbeach]

Hi,

Guys, thanks for all the help & information.

Most JFETS have a rather broad range of IDSS & also Vgs(off) in any given model. Until I get the chance to test, group, & choose the actual devices to be used out of the handfuls I have, I had thought it best to TEMPORARILY use a variable resistor for the drain (or plate) resistors for breadboard test purposes. In practice & for the actual final circuits, I planned to use regular set resistor values for the drain resistors as you all recommend. I'll now include trimpots for source (or cathode) resistors in the breadboard testing version. Thanks for that suggestion.

The 10 Meg resistor on the INA103 amp's output is indeed major overkill. The JFET gate needs some reference to ground & that easily can be from 10 Megs to 500K or less (at least in most of the schematics I've been studying). I'm sure the INA103 output would be happy to deal with anything in that range or somewhat lower. The resistor is there primarily for the benefit of the JFET gate (or plate) input. I've got a few dozen 10 Meg resistors piled up & just chose to use that value from convenience.

Each of the JFET types shown in the schematic have a different Vgs(off) rating. This characteristic sets what the maximum input signal voltage can be before causing clipping, plus this value also affects the gain for the device. I chose the JFET variety to avoid input clipping at the various stages ... the 1st JFET stage can have a smaller Vgs(off) value than the next JFET stage. So, that's the rationale for having three different JFET devices. And there isn't, nor is there likely to be, any production or maintenance staff to be worried about.

Of course, you're 100% correct about the BJT emitter resistor. Thanks for pointing that out. I was going "trimmer crazy".

Gus, with a 6k to 7k drain resistor for the 1st JFET voltage gain stage I would expect to need to use at least a 50k, and even better, a 100k volume pot after it. Indeed, that would preclude the need for a lower output impedance provided by the source follower. Thanks for the recommendation.

I've used 100 ohm series resistors in the RC network for isolating the power rails in past projects & will change the 10 ohm value in the schematic to reflect that. Thanks for pointing that out too. I have a large pile of 35v 220 uF low impedance electolytics lying around so I see no real need to lower that value - except I will probably add some .1uF film bypass caps to these elecrolytics.

Overall, I thank you guys for your patience with a virtual newbe & for your very insightful suggestions. Most of my experience has been in designing with opamps - so this discrete approach is new to me & I'm trying to learn about this stuff by reading & looking at schematics.

Skip

 

[Guest]

Did you consider to go without any source (emitter, cathode) followers?

However, if you like "broken glass" type of colorations it is the way to go...

 

[Gus]

Sbeach(added)

Reread PRRs post there is a good hint in it that you might have missed about the -24 and fets

Edited

 

[Minion]

Hi, The INA103 also has an output Gain stage that can be easilly implemented...It has a Gain range of between 1 and 10 on top of the Pre gain stage so It might be something that you might consider for adding some extra gain......

I have done a few designs useing the INA103 one of which was remotely simular to your design.....
I also did one design that had a Tube gain stage after the INA103 useing two 6418 sub mini tubes, I haven"t built that one yet but I did etch the board but haven"t gotten arround to stuffing it yet.....

Looks like an interseting design though.....

Cheers

 

[Guest]

[quote author="Gus"]Reread PRRs post there is a good hint in it that you might have missed about the -24 and fets[/quote]

? :shock:

 

[PRR]

> trimpots for source resistors in the breadboard

That's where the variation "is". The drain resistor should be sized to the load, not the device. The source resistor must be sized to the device's parameters.

If you take the source resistor to a large negative voltage, much larger than threshold voltage variation, you "fix" the device current against large variation of device parameters.

> The JFET gate needs some reference to ground .... I'm sure the INA103 output would be happy to deal with anything in that range

When the INA is doing its thing, pin 11 senses pin 10's voltage and forces it to equal pin 7's voltage plus the amplified signal. Pin 10 will sit at zero volts DC with less than 100 (probably less than 1) ohms DC impedance, and do so despite many milliAmps of load; the picoAmps of FET gate leakage will not change that. The only reason you might want a resistor there is so you can pull the INA out of socket and test the naked FETs.

Put it in, it does no harm at all, except waste six cents.

 

[Guest]

[quote author="PRR"]> trimpots for source resistors in the breadboard

If you take the source resistor to a large negative voltage, much larger than threshold voltage variation, you "fix" the device current against large variation of device parameters.

[/quote]

...limiting output current (that may be good) and introducing unpleasant distortions due to rectification on source loaded by capacitor (that is bad). Asymmetrical dynamic resistance + capacitance applied to bias = "farting distortions".

However, if time constant is small it is called "transistor sound".

 

[Gus]

Wavebourn

the post was for sbeach

 

[sbeach]

Hello,

Gus, thanks for pointing it out but yes I did see (and understand) PRR's tip about using the -24 rail feeding a 22k source resistor. I'm intrigued & plan to breadboard this circuit approach & play with it a bit before going further.

Here's another question for my edumacation: For a common source JFET amplification stage, in determining what current level to choose for the JFET drain (and therefore what value resistor to use there), do you need to choose a current value that is at or below the IDSS of the actual JFET in the circuit? I would think so but greater minds with more experience are hopefully looking on & willing to comment. Thanks in advance.

Skip

 

[Guest]

[quote author="sbeach"]Hello,

Gus, thanks for pointing it out but yes I did see (and understand) PRR's tip about using the -24 rail feeding a 22k source resistor. I'm intrigued & plan to breadboard this circuit approach & play with it a bit before going further.
[/quote]

Warning: instead of stable bias you will get very floating bias that depends on the level of the signal.

Here's another question for my edumacation: For a common source JFET amplification stage, in determining what current level to choose for the JFET drain (and therefore what value resistor to use there), do you need to choose a current value that is at or below the IDSS of the actual JFET in the circuit? I would think so but greater minds with more experience are hopefully looking on & willing to comment. Thanks in advance.

Skip

I always look in datasheet for regions better in terms of mu, noises, linearity.

At IDSS is the best case in terms of biasing, if no feedback needed.

 

[PRR]

> Wavebourn ... the post was for sbeach

No, it was a public post, so that others could comment, correct, or disagree.
Wavebourn has strong opinions, apparently based on both theory and actual trials.

I'm not sure I agree with Waveborn's points. "limiting output current" seems moot for the case of small-signal amplifiers. "Farting" is a major problem in over-driven guitar amps, and is generally due to the points he makes. Maybe my understanding of how to use a "Mic Pre" is old-fashioned. I think the preamp should capture without injury (to borrow a phrase), used far below its straining-point. Any "color" should be added later, at least a dedicated stage and very preferably in a mix-down after a clean original has been captured to tape.

I sure do not get the point of "very floating bias" unless the stage is in gross overload. No, I would not use that design for a "strong color amp". If Idss is much larger than bias current, and you beat the pulp out of the input, it is just going to turn itself off. Which I guess is Wavebourn's point.

Sbeach will just have to make up his own mind, of course.

> do you need to choose a current value that is at or below the IDSS of the actual JFET in the circuit?

Idss is the current for a small Drain voltage (enough above triode-region that the exact value hardly matters). For practical purposes, it is the maximum current of the device: you may get a little more with Gate positive of Source, but you can only go 0.6V positive before Gate current becomes a flood, and the increase from 0.0V to 0.5V is less than your inaccuracy of Idss knowledge.

For a high power output stage which must work with low impedance or low supply voltage, your maximum Class A idle current is half of Idss. If Idss is 20mA, idle at 10mA and swing 0mA to 20mA.

For a small signal stage with low load impedance: you can bias the same, or you can bias to a very large fraction of Idss. Like if you only need 1mA peak swing, you could bias to 19mA, swing 18mA to 20mA. Idling richer increases gain by about the square-root of current, so you'd expect gain to rise 30%-40%. That is, if you do not change your DC load resistor. If you reduce it to get increased current at the same supply voltage: Gm rises almost 40%, Rl falls to half, gain falls to 70%.

If your load resistance is high, you will get maximum voltage gain from an FET R-C coupled amp with the lowest idle current which will pull the load. Rl scales directly with current, Gm with square-root of current, so 10 times less current gives 3 times more voltage gain. Just as with vacuum tubes (but not BJTs): reduce current to increase voltage gain.

That is until your DC Source resistor approaches your load impedance. If it is another FET: the DC resistance may be 2Gigs. We commonly use a 1 Meg resistor too. But in audio we always have Stray Capacitance sucking our signal. Assume a 12AX7 has 100pFd on its grid. Big MOSFETS can be far more. Small JFETs have low capacitance, but Miller multiplies the Drain-Gate pFd, and a non-teeny layout can add 30pFd of strays. 10K+30pFd node impedance gives "only" 500KHz response. 100K+30pFd will start to trim the audio band. 100K may be too much if you are running wires to pots.

 

[sbeach]

Thank you all for the help & education!

PRR - perfectly logical, understandable & very helpful post. Yet a further question:

Given a small signal circuit, what may be the expected sonic characteristics, if any, of setting the JFET "idling" point at half the supply voltage compared to setting it 2/3rds or more "richer"? I would guess that the "color" of the circuit would be different only if driven fairly hard, but could you (or someone) describe the effect on sonics between the range of operating points from 1/2 to around 7/8 the supply voltage? Thanks again.

Skip Beach

 

[Guest]

PRR, English is not my native language, sorry. I mean, current through the load is limited by current supplied by big resistor in "tail" with relatively high voltage on it. Yes, due to shunt capacitor presence negative current peaks will be higher, but charging the capacitor they will shift bias so an average current will decrease. No matter high small are load capacitors, but anyway they present and cause bigger bias shift on highs. I don't think that floating bias that depends on the signal level is what do we need, no matter how small is the signal. Small distortions tend to accumulate through the signal path, so l prefer to design each stage such a way so it gives as less as possible audible innatural distortions.