Stereo AD/DA with S/PDIF or AES-EBU needed. Evaluation boards any good for this?

[ppa]

Personally, I am developing a DAC unit using DOA's in the analog stage and a PCM1794 in the DA stage. I am just asking to a PCB company to make the boards.
I preferred to use discrete components in the analog stage, there are only a few of DAC using them. I will use inside it my new fet based DOA.
BTW I am just near to send two of this DOA to Kindston as I have promised to him in the recent past.

The problem of a discrete analog stage is the power required for its running, as it is obvius.

 

 

[living sounds]

Personally, I am developing a DAC unit using DOA's in the analog stage and a PCM1794 in the DA stage. I am just asking to a PCB company to make the boards.
I preferred to use discrete components in the analog stage, there are only a few of DAC using them. I will use inside it my new fet based DOA.
BTW I am just near to send two of this DOA to Kindston as I have promised to him in the recent past.

Sounds interesting! Any thoughts about making it availible as a DIY project? ;-)

 

[millzners]

It's my understanding that a fully discrete converter needs lot's of space, ventilation, time to heat up, has inherently high latency and is prohibiltly expensive not least because the components need matching at a crazily high standard in order to achieve a measured performance comparable to chip based solutions. I think the Lavry Gold has special heating circuitry in order to maintain the required temperature at all time during use. It sounds totally awesome anyway, smooth as silk, not "digital" at all.


I had a talk today with an engineer of a higher end converter manufacturer who blatantly told me that in his opinion engineers need to turn off their measuring equipment once in a while and use their ears to actually find things out. He tests the analog circuitry and all the op amps by ear to find the best sounding solution. I like that.

I spoke with a senior engineer about that R2R ladder network for the DA conversion, he said that after around 16 bits you run out of accuracy even with 0.01% thin film resistors and basically have to turn to getting a set of resistors all etched on the same piece of silicon, or whatever it is they use.  That way they're all from the same piece of material made under the same conditions -- things like that make it not only expensive to produce but nearly impossible to even get a design off the ground. 

We also had a discussion about the clocks in converters being especially overlooked when people are comparing DAC's.  A clock with crap for phase noise (jitter) that isn't frequency stable over temperature isn't going to give you favorable results even if you have prestine analog circuitry.  Most cheap or even middle of the road converters just throw a cheap cyrstal or two in there, which is a severe performance limitation.

I'd sure feel uncomfortable justifying a technical decision based on my perception, so I can easily see why they'd cling so tightly to their data and measurements. 

 

[living sounds]

I spoke with a senior engineer about that R2R ladder network for the DA conversion, he said that after around 16 bits you run out of accuracy even with 0.01% thin film matching resistors and basically have to turn to getting a set of resistors all etched on the same piece of silicon, or whatever it is they use.  That way they're all from the same piece of material made under the same conditions -- things like that really add to the cost and complexity too.

And this way you've got yourself an integrated circuit after all, at least of sorts...

 

[abbey road d enfer]

I wonder...Is the idea here of getting the best performance or getting rid of IC's for the sake of it?

 

[millzners]

I wonder...Is the idea here of getting the best performance or getting rid of IC's for the sake of it?

For my own education, I'm trying to discover where the weakest links in the chain really are.  You read a lot about the analog stage because that's something your average DIY'er can attack.  But would upgrading the crap crystal to a top of the line TCXO yield more audible difference?  Is there a limit that these cheap old chips can really achieve before you hit the wall, or is the chip really the least important component?

I intend to take that ART DIO to the limit and find out, simply because I have the schematic and it's easy to work on. 

 

[abbey road d enfer]

For my own education, I'm trying to discover where the weakest links in the chain really are.  You read a lot about the analog stage because that's something your average DIY'er can attack.

And probably where there is the least to improve.

But would upgrading the crap crystal to a top of the line TCXO yield more audible difference?

The "crap crystal" is probably good enough for another order of magnitude in performance, unless it is integrated in a lousy design. One has to deploy a lot of efforts to make a crappy crystal clock (perhaps with help from a bean counter).  :-[ A much more likely terrain for improvement is the clock recovery from external sync. It has been demonstrated times and again that the PLL circuits used in many cheap converters leave a lot to be desired.

Is there a limit that these cheap old chips can really achieve before you hit the wall, or is the chip really the least important component?

There is definitely a limit to any converter chip, that no external tweak could help transcend. You seemed to agree with that when you compared the M-Audio and the ART.
These "old" chips are not that bad; testimony is in the recordings done with the ADC1 and 8824, they stand the test of time. Improvements in converter chips affect the perceived quality of sound very marginally; what's the difference between 114dB dynamic range today and 108dB yesterday? Nothing to write home about in practical terms. Today's chips have lower consumption, easier interfacing but audio performance is about the same, still hitting on the same old analog limitations (Johnson noise).

I intend to take that ART DIO to the limit and find out, simply because I have the schematic and it's easy to work on.

Please, let us know your findings. There's a whole industry there, trying to convince  poor bastards that their doomed cheapo converter can be made to equal a Lavry or a Prism just by changing a few opamps and the PSU, as if putting a Marelli injection in a Pinto would turn it in a Ferrari.

 

[millzners]

For my own education, I'm trying to discover where the weakest links in the chain really are.  You read a lot about the analog stage because that's something your average DIY'er can attack.

And probably where there is the least to improve.

But would upgrading the crap crystal to a top of the line TCXO yield more audible difference?

The "crap crystal" is probably good enough for another order of magnitude in performance, unless it is integrated in a lousy design. One has to deploy a lot of efforts to make a crappy crystal clock (perhaps with help from a bean counter).  :-[ A much more likely terrain for improvement is the clock recovery from external sync. It has been demonstrated times and again that the PLL circuits used in many cheap converters leave a lot to be desired.

Is there a limit that these cheap old chips can really achieve before you hit the wall, or is the chip really the least important component?

There is definitely a limit to any converter chip, that no external tweak could help transcend. You seemed to agree with that when you compared the M-Audio and the ART.
These "old" chips are not that bad; testimony is in the recordings done with the ADC1 and 8824, they stand the test of time. Improvements in converter chips affect the perceived quality of sound very marginally; what's the difference between 114dB dynamic range today and 108dB yesterday? Nothing to write home about in practical terms. Today's chips have lower consumption, easier interfacing but audio performance is about the same, still hitting on the same old analog limitations (Johnson noise).

I intend to take that ART DIO to the limit and find out, simply because I have the schematic and it's easy to work on.

Please, let us know your findings. There's a whole industry there, trying to convince  poor bastards that their doomed cheapo converter can be made to equal a Lavry or a Prism just by changing a few opamps and the PSU, as if putting a Marelli injection in a Pinto would turn it in a Ferrari.

And I'm really skeptical of any of those mods, my goal isn't to improve my cheap DAC to make it sound like a Lavry (that's crazy), it's to learn about what is it exactly that is limiting the thing.  What can I actually hear, despite what I can measure. 

Here's a link just read:
http://www.audiocraftersguild.com/AandE/npt.on.jitter2.htm

"Dr. Hawksford reports that a 1 LSB error of a 15kHz signal results from only 0.324 nS of clock error"

Well using this: http://www.jittertime.com/resources/pncalc.shtml

to convert phase noise to jitter yields numbers like 8ps RMS for a good crystal, whereas a good TCXO is more like 0.6ps RMS.  Well right there you're already 1 orders of magnitude below the jitter needed to get a bit error at 15kHz with a crystal and 2-3 orders of magnitude below that for a TCXO...  So like you said it may be a waste of time, or maybe those crystals in the DAC aren't "good".  I can't find phase noise specs for a bad crystal, they don't publish them.

And to your point about the PLL performance, if I upgrade the onboard clock and don't sync to an external SPDIF, it should bypass the PLL you were referring to, right?

 

[fabriciom]

A Lavry AD/DA DIY project. That would be awesome!

 

[abbey road d enfer]

http://www.audiocraftersguild.com/AandE/npt.on.jitter2.htm
"Dr. Hawksford reports that a 1 LSB error of a 15kHz signal results from only 0.324 nS of clock error"

Everything they say ther is true. However, please note that most of it relates to "media-induced jitter", which is something that happens only when clock and data are transmitted on the same physical transmission media, which is the case of S/PDIF and AES3 in particular. In pro and semi-pro applications, it is almost always possible to transmit clock separately from data, generally via WC or AES black.
It would take a terrible designer or a terrible crystal to produce jitter in the order of nanosecond. But a poor PLL can.

And to your point about the PLL performance, if I upgrade the onboard clock and don't sync to an external SPDIF, it should bypass the PLL you were referring to, right?

Correct. You want your ADC to be the clock master, right? Then you will need to sync your recorder/DAW but the requirements are much less stringent. Once the signal is digitized, it can be transmitted and recovered even with huge jitter.

 

[millzners]

http://www.audiocraftersguild.com/AandE/npt.on.jitter2.htm
"Dr. Hawksford reports that a 1 LSB error of a 15kHz signal results from only 0.324 nS of clock error"

Everything they say ther is true. However, please note that most of it relates to "media-induced jitter", which is something that happens only when clock and data are transmitted on the same physical transmission media, which is the case of S/PDIF and AES3 in particular. In pro and semi-pro applications, it is almost always possible to transmit clock separately from data, generally via WC or AES black.
It would take a terrible designer or a terrible crystal to produce jitter in the order of nanosecond. But a poor PLL can.

And to your point about the PLL performance, if I upgrade the onboard clock and don't sync to an external SPDIF, it should bypass the PLL you were referring to, right?

Correct. You want your ADC to be the clock master, right? Then you will need to sync your recorder/DAW but the requirements are much less stringent. Once the signal is digitized, it can be transmitted and recovered even with huge jitter.

Well I had another discussion with a senior engineer about the schematic.  Basically, and not surprising, there is no major weak link.  Everything is on par with everything else.  So for example:

Well how about I upgrade the crystal?

"The slower HC00 gate isn't going to give you much better phase noise than you've getting from that crystal, especially the floor.  Your close-in phase noise will improve somewhat, but there's a limit to what you can do with that gate."

Well how about I upgrade the gate?

"Well you'd need to find one with faster edge rates to improve your noise floor because it will get you from 0 to 1 faster and spend less time in the middle, but that may hurt you b/c faster edge rates spray RF all over the place and the original design probably didn't account for that in their grounding scheme."

Ok well what is the weakest link?

"It looks like everything is designed to work together so there's no one really terrible element to that design."

So there you have it.  I acquired an OCXO for the 96kHz clock anyway, if nothing else I'll improve the clock in the DIO and sync the M Audio to it.  Who knows maybe I'll get lucky and it'll actually help.

 

[Kingston]

Personally, I am developing a DAC unit using DOA's in the analog stage and a PCM1794 in the DA stage. I am just asking to a PCB company to make the boards.

Very interesting. Is this a commercial thing, or are you planning on offering this project here on the forum? What kind of digital input options did you choose?

 

[ppa]

Personally, I am developing a DAC unit using DOA's in the analog stage and a PCM1794 in the DA stage. I am just asking to a PCB company to make the boards.

Very interesting. Is this a commercial thing, or are you planning on offering this project here on the forum? What kind of digital input options did you choose?

for this moment is only a project.
I have designed a 2d PLL with VCXO's with very low jitter, but in this moment the DAC unit has not an automatic sample frequency detector so the sound engineer should select the right sample frequency on the panel. I have two recording studio interested in buying it the same, but I don't know if this manual selection is a problem or not.
I repeat for this moment is only a project.


It's a stereo dac and it uses AES/EBU input, spdif coaxial input, ext. W clock input.
Maybe I will add an USB input.



 

 

[ppa]

I would add that for a very low jitter is necessary a good layout, I seen a very expensive dac unit that has a 1pS rated VCXO  with a measured jitter of 52pS on the WC.

Moreover, regarding cheap DAC units, the most used receiver is the CS8416 as in the cheap as in the expensive gears. The difference are often that the second ones have a 2d PLL to reduce the jitter from the source.
I have read on the web that CS8416 has a lot of intrinsec jitter , this is false.
The CS8416 has an intrinsec jitter a lot less than the 200pS in its datasheet, it's less than 50 pS p-p for my personal experience. The matter is that the layout and power supply should be good to having a good jitter performance.
So if the source have has very low jitter it's possible even with a cheap dac having good jitter performances.

 

[millzners]

I would add that for a very low jitter is necessary a good layout, I seen a very expensive dac unit that has a 1pS rated VCXO  with a measured jitter of 52pS on the WC.

Moreover, regarding cheap DAC units, the most used receiver is the CS8416 as in the cheap as in the expensive gears. The difference are often that the second ones have a 2d PLL to reduce the jitter from the source.
I have read on the web that CS8416 has a lot of intrinsec jitter , this is false.
The CS8416 has an intrinsec jitter a lot less than the 200pS in its datasheet, it's less than 50 pS p-p for my personal experience. The matter is that the layout and power supply should be good to having a good jitter performance.
So if the source have has very low jitter it's possible even with a cheap dac having good jitter performances.

I agree, the keys to phase noise/jitter are the little things with the layout, I've seen sloppy layouts and careful layouts using the same basic components yield very different results.  I wonder though how much jitter can be heard, where's the threshold of being able to detect it.  For example I wonder how much worse sounding the same DAC is with 200pS vs 2pS jitter.

I hope to learn a little bit about this as I work through kludging in an OCXO into the DIO circuit.  I know that there's a limit to how much of a difference it can make in the quality of the clock, and for me it will help define just how much jitter plays a role in these low-end DAC's.

 

[ppa]

I hope to learn a little bit about this as I work through kludging in an OCXO into the DIO circuit.  I know that there's a limit to how much of a difference it can make in the quality of the clock, and for me it will help define just how much jitter plays a role in these low-end DAC's.

seems that having in a clock source 10pS of jitter or below, as for example 1pS, is the same thing for the sound look of a dac in most cases, but also 20pS are often not udible.
However for each board there is a dated limit jitter value (a threshold) that below it the performances are however not increased 

 

[HerculesVR]

Hello ppa , you know 1pS phase jitter (phase noise 1Hz - 100kHz test bandwidth) ultra high cost, only VCOCXO or VCTCXO(approximate), but VCOCXO and VCTCXO both bad pull range - less than +/-10ppm. Good VCXO or LC-VCO is about 20pS and it is enough for pro audio application, good phase noise - better than -50dBc @1Hz / -75dBc@10Hz and good APR - more than +/-100ppm, top grade LC-VCO even +/-2500ppm.  AES12-id-2006 jitter test standard is easy get good vision spec because TIE test @100Hz high pass filter.

Phase noise test for digital audio, less than 10Hz offset frequency is very important for listen. NO matter over 100kHz offset frequency phase noise - this band not affect audio performance. Many AD/DA manufacturer dun give us MCLK which fill DAC chip phase noise test plot - you know low cost phase noise measurement instrument still more expensive than audio precision 2722. Test bandwidth always cheat us.

Yeap DAC layout is most important. I dun think discrete OPA is good for high quality DAC design   Such as ES9018/AD1955 design.

Except that you have phase noise measurement instrument, otherwise no need excessive pay close attention to jitter,  just choose a good DIR such as AK4118A. You must choose VCXO which provide you phase noise test plot if you want to building 2nd PLL. BICK and LRCK and SDATA jitter analyzer you should use serial data analyzers such as LeCroy SDA, it is also expensive.  JTEST is low cost jitter measurement and easy to using.

Anyway, good luck.

 

[ppa]

thanks HerculesVR,

my 2d pll was tested with a 5Ghz oscilloscope and performed with 17.5 pS p-p of jitter so it seems a great value.  It uses two VCXO's rated for 1pS rms of jitter.  It has a corner frequency of 10Hz to reduce the source jitter.

My AES/EBU receiver as an intrinsic jitter (mesured with the same 5Ghz oscilloscope) of 45 pS p-p  on w clock that seems a great value. 

 

[ppa]

I have designed an SRC too , I will see if it performs better than the PLL,

In the 2d PLL I use an 74VHC9046 as phase detector and VHC standard CMOS logic IC's, I use only CMOS logic to reduce a lot the digital noise, moreover in each IC's I use only some parts to reduce the digital noise. 

 

[ppa]

regarding jitter is important reduce as well as possible the interference between the digital sections by power supply, moreover is important that the digital noise doesn't go by the PSU to the analog sections. The analog section desn't see digital noise.

Moreover, the VCXO's and the phase detector should have a very clear power supply voltage.

In my DAC each digital section has its dedicated PSU line and I use SMD RF grade ceramic caps to decupling these ones.