Stereo AD/DA with S/PDIF or AES-EBU needed. Evaluation boards any good for this?

[HerculesVR]

Hi ppa.

Actually phase noise is best function about jitter test, high-speed oscilloscope is not perfect.

SRC is sound quality killer, you know no one state-of-the-art AD/DA working under SSRC/ASRC. You can check Xilinx application note xapp1014 or xapp514 fr more tech detail. PLL re-clock much better than SRC if good design.

This is good technique note about high quality AD/DA design, author is Prism Sound CTO Ian Dennis.
http://resources.prismsound.com/tm/Converter_performance_challenges.pdf

74HCT9046 is good PD but only 5V-TTL. You can try high speed isolator such as ADUM1400C for reduce digital noise transfer to DAC Chip, digital isolator is also good level transceiver.

Yeap PSU is very important to high quality AD/DA design, multi stage series regulator is best choose, good series regulator noise less than 5uV.

Jitter is important but can not be ignored is analog section design, analog is the key of quality.

 

[millzners]

Hi ppa.

Actually phase noise is best function about jitter test, high-speed oscilloscope is not perfect.

SRC is sound quality killer, you know no one state-of-the-art AD/DA working under SSRC/ASRC. You can check Xilinx application note xapp1014 or xapp514 fr more tech detail. PLL re-clock much better than SRC if good design.

This is good technique note about high quality AD/DA design, author is Prism Sound CTO Ian Dennis.
http://resources.prismsound.com/tm/Converter_performance_challenges.pdf

74HCT9046 is good PD but only 5V-TTL. You can try high speed isolator such as ADUM1400C for reduce digital noise transfer to DAC Chip, digital isolator is also good level transceiver.

Yeap PSU is very important to high quality AD/DA design, multi stage series regulator is best choose, good series regulator noise less than 5uV.

Jitter is important but can not be ignored is analog section design, analog is the key of quality.

It's refreshing to hear someone talk in terms of phase noise, I think jitter can be a very hazy subject because it can be calculated several different ways to produce different values.  Phase noise never lies, and anything from a noisey regulator to a poorly chosen PLL loop filter will show up clear as day where a jitter number may conceal those issues.

 

[ppa]

Yes, as state of the art DAC's, I know only the Forsell's DAC's that use ASRC systems , the other state of the art dac's use PLL's only.

Regarding the 74HCT9046 , yes, it is a 5V IC but the PCM1794 is 5V tollerant and the CS8416 has a power supply pin (VL pin) to have 5V on its outs. the other logics are 5V supply powered.

Regarding optocoupler it is a good thing even if optocouplers often increase jitter a bit.

I use one REG101 regulator for the CS8416 analog section, one for the VCXO's and another one for the 74HCT9046 since it is the phase detector in the 2nd PLL.
Before of these REG101 there are LM317 regulators as pre-regulators on board.

I am using VCXO's from Crystek. 

 

[ppa]

It's refreshing to hear someone talk in terms of phase noise, I think jitter can be a very hazy subject because it can be calculated several different ways to produce different values.  Phase noise never lies, and anything from a noisey regulator to a poorly chosen PLL loop filter will show up clear as day where a jitter number may conceal those issues.

the matter is that in this moment I have only an high speed oscilloscope for jtest

 

[ppa]

74HCT9046 is good PD but only 5V-TTL. You can try high speed isolator such as ADUM1400C for reduce digital noise transfer to DAC Chip, digital isolator is also good level transceiver.

I have read the ADUM1400C datasheet that is not an optocoupler but a micro-trasformer coupler it
does not reduce the jitter.