thumping with Self's mute block

[electronicpresskit]

Hello everyone!

I've got a slightly modified version of Douglas Self's mute block cooked up and it's working nicely most of the time. The problem is that I get a thump on unmute if there is significant gain change to the input signal while it's muted.

For example, I input a +/-1.6v triangle wave, mute it, reduce the gain to .8v, then unmute it and I see/hear a negative voltage spike in the audio signal. If I don't change the gain and just mute/unmute there is no thump.

Notable differences to Self's schematic are:

U5C and U5D are used as complementary logic drivers for the j111's.
Rp has been removed since control circuitry never goes above 0v.
R136 was reduced to 300k to improve offness.

If anyone can shed some light on this, it will be greatly appreciated!

Thanks!

epk

 

[JohnRoberts]

Hello everyone!

I've got a slightly modified version of Douglas Self's mute block cooked up and it's working nicely most of the time. The problem is that I get a thump on unmute if there is significant gain change to the input signal while it's muted.

Looks complicated for a mute but probably works.

Thump suggests DC...  With the signal muted do you measure any DC voltage change on top of C115 as you vary the signal level?

For example, I input a +/-1.6v triangle wave, mute it, reduce the gain to .8v, then unmute it and I see/hear a negative voltage spike in the audio signal. If I don't change the gain and just mute/unmute there is no thump.

Notable differences to Self's schematic are:

U5C and U5D are used as complementary logic drivers for the j111's.
Rp has been removed since control circuitry never goes above 0v.

don't know what a Rp is?

R136 was reduced to 300k to improve offness.

? R136 forms a voltage divider with R134 so reducing that resistance makes the gate voltage less negative when turned off (offness?) If anything that could hinder pinching off Q6 . A quick glance at a data sheet suggests a cut off voltage range of -3V to -10V . If the gate voltage is marginal to pinch off the JFET,  audio signal on drain could modulate on resistance, maybe half wave rectify.

I repeat check voltage on C115. maybe increase R136 to improve it's offness.... 8)

If anyone can shed some light on this, it will be greatly appreciated!

Thanks!

epk

I've done a number of mutes over the years, but never like that. YMMV and many ways to skin those cats.

JR

 

[electronicpresskit]

Thump suggests DC...  With the signal muted do you measure any DC voltage change on top of C115 as you vary the signal level?

will check this tomorrow when I'm in front of it.

don't know what a Rp is?

it's a high value R used to slightly positively bias the jfet above 0v to reduce on resistance. it's not applicable here as my control circuit switches between 0v and -10v instead of +/- 7.5v as Douglas Self's example (with J112) is originally.

? R136 forms a voltage divider with R134 so reducing that resistance makes the gate voltage less negative when turned off (offness?) If anything that could hinder pinching off Q6 . A quick glance at a data sheet suggests a cut off voltage range of -3V to -10V . If the gate voltage is marginal to pinch off the JFET,  audio signal on drain could modulate on resistance, maybe half wave rectify.

hehe, sorry for the confusion! I started with 680k here but the mute did not attenuate the signal enough. reducing it to 300k provided satisfactory attenuation. Because the attenuation occurs while Q6 is open and shunting to GND, it means the control signal is at 0v and the diode is not conducting. So in that case the gate is closer to 0v with 300k instead of 680k, resulting in more attenuation of the signal. At least that's my theory 

Thanks!

 

[JohnRoberts]

Thump suggests DC...  With the signal muted do you measure any DC voltage change on top of C115 as you vary the signal level?

will check this tomorrow when I'm in front of it.

don't know what a Rp is?

it's a high value R used to slightly positively bias the jfet above 0v to reduce on resistance. it's not applicable here as my control circuit switches between 0v and -10v instead of +/- 7.5v as Douglas Self's example (with J112) is originally.

Since I am not familiar with what Self did it's hard for me to comment on his original design.  FWIW a J112 has a tighter gate control region (-1V to -5V) So will actually work reliably from 7.5V gate drive.

? R136 forms a voltage divider with R134 so reducing that resistance makes the gate voltage less negative when turned off (offness?) If anything that could hinder pinching off Q6 . A quick glance at a data sheet suggests a cut off voltage range of -3V to -10V . If the gate voltage is marginal to pinch off the JFET,  audio signal on drain could modulate on resistance, maybe half wave rectify.

hehe, sorry for the confusion! I started with 680k here but the mute did not attenuate the signal enough. reducing it to 300k provided satisfactory attenuation. Because the attenuation occurs while Q6 is open and shunting to GND,

During mute Q5 is open (high impedance pinched off) and Q6 is turned on (low impedance, conducting). . R136 only needs to discharge the Q6 gate capacitance  (5 pF) to 0V.

The odd DC biasing scheme of Q6 source from output of U5B could cause some weird race condition if it holds that source at some other Dc voltage than 0V, but let's assume it works.

There should be no difference between 300k and 600k discharging 5pF. But maybe put a scope probe on there to see what is happening dynamically.

JR

it means the control signal is at 0v and the diode is not conducting. So in that case the gate is closer to 0v with 300k instead of 680k, resulting in more attenuation of the signal. At least that's my theory 

Thanks!

Unless D25 has unusual leakage (or is backwards) the value of the R to ground should not affect DC voltage there.

JR

 

[analogguru]

It can be done without all of these problems.  Have a look at the switching circuit of the Studer A807.

 

[electronicpresskit]

Thump suggests DC...  With the signal muted do you measure any DC voltage change on top of C115 as you vary the signal level?

the text below was due to an invisible (to my eye) solder bridge between gate and source of Q6. there is now no DC voltage here.

Yes.

While muted and with the signal present, as gain is reduced we get a +70mv DC offset that fades out over several seconds. As gain is increased we get a -70mv DC offset  that fades out over several seconds.  This is with a gain change rate = as fast as my hand can move the pot. Slower gain change rate yields lower DC offset values.

[quote author=JohnRoberts]
The odd DC biasing scheme of Q6 source from output of U5B could cause some weird race condition if it holds that source at some other Dc voltage than 0V, but let's assume it works.
[/quote]

Pin 8 of U5C switches between -130mv and -10.67mv.

[quote author=JohnRoberts]
There should be no difference between 300k and 600k discharging 5pF. But maybe put a scope probe on there to see what is happening dynamically.
[/quote]

Attached is what the Q6 gate looks like at unmute.

Thanks,

epk

 

[electronicpresskit]

It can be done without all of these problems.  Have a look at the switching circuit of the Studer A807.

I had a look at the service manual for a few minutes and I didn't see a solution. I went with a Jfet method as I need a fast fade in/out for clickless muting.

Did I miss something in there that provides clickless muting?

Thanks!

epk

 

[JohnRoberts]

Mute circuits can and have been done effectively.

It is impossible to make then completely "clickless" since a fast mute that isn't coordinated with signal zero crossings will click depending on the instantaneous voltage of the signal being muted. (There are multiple techniques to mitigate that).

I am not sure I want to follow you down that rabbit hole without seeing the original design you "borrowed" from. You are getting an education,, figure out why the DC voltage is changing... (hint rectification is going on somewhere).

JR

PS: when you put a scope probe on a high impedance node, the scope will provide a DC path to ground  (generally megohms).

PPS: I've done these a number of different ways over the years and even made noise gates typically using JFET shunts (not in series).  I have also used transfer gates (like CMOS 4016)  in series and shunt for electronic line level signal switching inside consoles. 

 

[analogguru]

It can be done without all of these problems.  Have a look at the switching circuit of the Studer A807.

I had a look at the service manual for a few minutes and I didn't see a solution.
......

Studer A807 service manual, chapter 7, page 27,  upper left corner: the circuit around the 4053

Did I miss something in there that provides clickless muting?

As John Roberts already wrote:
[quote author=JohnRoberts]It is impossible to make then completely "clickless" since a fast mute that isn't coordinated with signal zero crossings will click depending on the instantaneous voltage of the signal being muted. [/quote]

 

[Monte McGuire]

I'm working on a slightly similar soft switch circuit using series and shunt switches. In order to keep the JFETs at virtual ground, it's good to make the series and shunt switches overlap in time, so that the inverting input node does not go high impedance, placing the full signal voltage across the JFET. As long as one or the other switch is conducting, then the drains will be held at VE, and then little voltage will develop across the JFETs, preventing a number of problems.

The downside to this is that when both series and shunt switches are conducting, the noise gain of the output I/V amplifier U5B goes way up, depending upon the threshold voltages of the switch devices and the gate drive voltages. The TL074 used there has a pretty huge offset, so if that gets amplified by a noise gain of 10-100, then you'll get a DC thump during the period when the series and shunt switches overlap.

The circuit as drawn shunts the inverting node to an AC ground, established by the 33µF cap. In the steady state, the signal gets shunted to AC ground, but the DC gain isn't actually enormous when the Q6 is on. However, during changeover, the noise gain does go up temporarily, creating that pulse that decays exponentially as C115 charges.

C115, that 33µF cap to ground at the source of Q6, doesn't make sense to me. It should not be needed at all, as long as Q5 eventually switches off. I think it's there to mask the DC offset problem, rather than fix it. When the overall switch is off, Q5 needs to be fully off and Q6 needs to be fully on. If both are partly on, then you get that offset problem that is eventually masked by C115 as it slowly charges.

Ditch C115 and then R22 seems irrelevant too.

I haven't simulated the circuit, so I may be off, but as far as I can tell, that's what ought to happen, and the issue of overlap does need to be addressed. Check the gate drive voltages to make sure these switches overlap, but only temporarily. Overlap is good - it's a far better way to avoid switching clicks than zero cross switching, especially if you want to switch several channels at once. Zero cross is no guarantee of click-free switching - the slopes never match anyway, even if the DC levels do. Further, from my experience doing micro-edits in a DAW, it's possible to cut a lot of things together using a several millisecond crossfade. Sure, you get a little thump sometimes, but that can be optimized with the right crossfade time, and you never get a real click.

 

[JohnRoberts]

I'm working on a slightly similar soft switch circuit using series and shunt switches. In order to keep the JFETs at virtual ground, it's good to make the series and shunt switches overlap in time, so that the inverting input node does not go high impedance, placing the full signal voltage across the JFET. As long as one or the other switch is conducting, then the drains will be held at VE, and then little voltage will develop across the JFETs, preventing a number of problems.

as drawn the two fets turn off relatively faster than they turn on so should not both be on at same time (not a good thing for both to be on IMO).

audio signal voltage with both FETs off could interact with gate voltage.

A simpler way is to clamp the junction of the two fets to ground through anti-parallel diodes. That way when both JFETs are ope the voltage there can not exceed +/- 1 diode drop. When one fet or the other is conducting the voltage there should be 0V so diodes are high Z.

I am not suggesting you make this diode clamp change,,,  presumably the original circuit worked serviceably...

The downside to this is that when both series and shunt switches are conducting, the noise gain of the output I/V amplifier U5B goes way up, depending upon the threshold voltages of the switch devices and the gate drive voltages. The TL074 used there has a pretty huge offset, so if that gets amplified by a noise gain of 10-100, then you'll get a DC thump during the period when the series and shunt switches overlap.

The circuit as drawn shunts the inverting node to an AC ground, established by the 33µF cap. In the steady state, the signal gets shunted to AC ground, but the DC gain isn't actually enormous when the Q6 is on. However, during changeover, the noise gain does go up temporarily, creating that pulse that decays exponentially as C115 charges.

the fast off slow on, prevents both from being on at same time.

C115, that 33µF cap to ground at the source of Q6, doesn't make sense to me. It should not be needed at all, as long as Q5 eventually switches off. I think it's there to mask the DC offset problem, rather than fix it. When the overall switch is off, Q5 needs to be fully off and Q6 needs to be fully on. If both are partly on, then you get that offset problem that is eventually masked by C115 as it slowly charges.

Ditch C115 and then R22 seems irrelevant too.

I hate trying to tweak an already tweaked circuit... Self has a good reputation (doesn't he?) , his original circuit "should" work.

I haven't simulated the circuit, so I may be off, but as far as I can tell, that's what ought to happen, and the issue of overlap does need to be addressed. Check the gate drive voltages to make sure these switches overlap, but only temporarily. Overlap is good - it's a far better way to avoid switching clicks than zero cross switching, especially if you want to switch several channels at once. Zero cross is no guarantee of click-free switching - the slopes never match anyway, even if the DC levels do. Further, from my experience doing micro-edits in a DAW, it's possible to cut a lot of things together using a several millisecond crossfade. Sure, you get a little thump sometimes, but that can be optimized with the right crossfade time, and you never get a real click.

There are ways to mitigate clicks, but thats for the advanced class,,, stop the thumping first, IMO.

JR

 

[electronicpresskit]

Thanks everyone! There's a lot here that i'm processing.

The preview for one of Douglas Self's books shows most of his text about the mute block. The figure on page 417 shows the main circuit. The figure on page 419 shows the addition of C115 and R22 (as named on my schematic), and point 2 under "Dealing with the DC Conditions" on page 420 discusses them. Above the figure on 417 he also discusses overlap of the switching.

When I first built the block, I had not included C115 and R22. I had thumps all the time. After their addition, the thumps only occur on unmute, after a significant gain change happens while muted.

C115 somehow seems good to me but I don't understand what R22 is doing. I'm not yet fully understanding where the DC offset is coming from.

https://books.google.de/books?id=pVIdAAAAQBAJ&pg=PA414&lpg=PA414&dq=douglas+self+mute+block&source=bl&ots=9AJfR39RYa&sig=dJ7Nb1iPnnebP-mQBVz_9TIw6Yc&hl=en&sa=X&ved=0ahUKEwjV1vLq6fzKAhUJc3IKHe7JCGQQ6AEIIDAA#v=onepage&q=douglas%20self%20mute%20block&f=false

note that the preview limits the number of times a person can view it.

 

[PRR]

> preview for one of Douglas Self's books ...figure on page 417 shows the main circuit. The figure on page 419...
> note that the preview limits the number of times a person can view it.

More capricious than that. For me it will NOT show p.417.

I snagged p.419 and context.

However I hope _you_ have the whole book, because the intro and detail information may cover much more than we are likely to hit here with tiny peeks into the book. 

 

[Gareth Connor]

As far as I am aware, Self does not use TL074 (or any op-amp for that matter) as a drive for the FET gates.
He usually has FETs driven by 4011 CMOS logic.

 

[electronicpresskit]

> preview for one of Douglas Self's books ...figure on page 417 shows the main circuit. The figure on page 419...
> note that the preview limits the number of times a person can view it.

More capricious than that. For me it will NOT show p.417.

I snagged p.419 and context.

However I hope _you_ have the whole book, because the intro and detail information may cover much more than we are likely to hit here with tiny peeks into the book.

Oh wow, I didn't realize how squirmy it was about which data it shows. I do have the whole book but was trying to link to data already out there while respecting the original IP, but I'm not sure that's working.

 

[electronicpresskit]

As far as I am aware, Self does not use TL074 (or any op-amp for that matter) as a drive for the FET gates.
He usually has FETs driven by 4011 CMOS logic.

correct, and that's the main difference between his version and mine. He uses CMOS logic to drive J112's.

my context is in a mixer for modular synths with signals that can be +/- 10v, so I thought it was important to go for the better spec'd J111. I used the TL074 to boost my 5v logic to the needed levels for the J111.

 

[electronicpresskit]

it seems I had an invisible (to my eyes) solder bridge between gate and source of Q6. this was responsible for the DC that was decaying over several seconds at C115.

There is no longer any DC sitting on C115 while muted, however the main symptom is still present.

Attached shows pin 7 of U5B on unmute after turning the gain all the way down. If I wait a few seconds after turning the gain down to unmute, the glitch doesn't happen.

 

[electronicpresskit]

Looking at the attached image, we see the voltage at the gate of Q5 and Q6 on unmute. Zooming in, it appears that the swing begins within 500uS of each other. This seems like pretty good performance to me.

 

[electronicpresskit]

Gah! Q5, not Q6

by probing the gate on Q6, the thump disappears. This is of course adding a 1M to GND in parallel with R136 for a combined 230kR.

Since R136 is part of a voltage divider that drives the gate, it also reduces the offness of the mute a lot and makes it more like a strong dim. I might be able to find a compromise between 300k and 230k that makes it work well enough, but it still doesn't explain the behavior. I'd also rather have great performance than well enough.

 

[JohnRoberts]

by probing the gate on Q6, the thump disappears. This is of course adding a 1M to GND in parallel with R136 for a combined 230kR.

Since R136 is part of a voltage divider that drives the gate, it also reduces the offness of the mute a lot and makes it more like a strong dim. I might be able to find a compromise between 300k and 230k that makes it work well enough, but it still doesn't explain the behavior. I'd also rather have great performance than well enough.

I've seen circuits that lack a DC path start working with the scope probe attached.

Confirm that you don't have an open ground connection feeding R136?

JR