thumping with Self's mute block

[electronicpresskit]

I've seen circuits that lack a DC path start working with the scope probe attached.

Confirm that you don't have an open ground connection feeding R136?

JR

Yep, good suggestion. I actually started troubleshooting this problem by trying a 1M to GND in several different junctions with no luck.

R136 is indeed connected to GND.

Thanks!

epk

 

[electronicpresskit]

Gah! Q5, not Q6

by probing the gate on Q6, the thump disappears. This is of course adding a 1M to GND in parallel with R136 for a combined 230kR.

Since R136 is part of a voltage divider that drives the gate, it also reduces the offness of the mute a lot and makes it more like a strong dim. I might be able to find a compromise between 300k and 230k that makes it work well enough, but it still doesn't explain the behavior. I'd also rather have great performance than well enough.

 

[electronicpresskit]

The downside to this is that when both series and shunt switches are conducting, the noise gain of the output I/V amplifier U5B goes way up, depending upon the threshold voltages of the switch devices and the gate drive voltages. The TL074 used there has a pretty huge offset, so if that gets amplified by a noise gain of 10-100, then you'll get a DC thump during the period when the series and shunt switches overlap.

If I zoom in very closely I do see a few mv of DC on top of C115 if I adjust the gain while the mute is active.  We're talking only 4-8mv, so it's a bit hard to tell exactly how much with the noise that's on top of it.  The offset amount also increases with the gain of the signal, and how long the gain is high. The higher the gain, the more offset, but not if it's very quick, it needs to be sustained for a few seconds.

Could this amount of DC offset be due to dielectric absorption of the 33uF electrolytic (C115)?

the behavior of the DC offset matches what I understand about the behavior of dielectric absorption, and maybe as Monte suggests the DC is then amplified 10x's creating the thump that lasts about 11ms (compared to the 20ms xfade).

 

[JohnRoberts]

If I zoom in very closely I do see a few mv of DC on top of C115 if I adjust the gain while the mute is active.  We're talking only 4-8mv, so it's a bit hard to tell exactly how much with the noise that's on top of it.  The offset amount also increases with the gain of the signal, and how long the gain is high. The higher the gain, the more offset, but not if it's very quick, it needs to be sustained for a few seconds.

Can I ASSume that when you say gain, you mean level?

When mute is active Q6 is conducting and Q5 is open?  Voltage on C115 should be same as output of U5B (is it?).

If there is a DC voltage change that suggests rectification is occurring somewhere.

Could this amount of DC offset be due to dielectric absorption of the 33uF electrolytic (C115)?

No...  Dielectric absorption is caused by the physical construction of a capacitor where the internal capacitance is spread out or distributed inside with resistances between effective regions of capacitance. The model for this looks like a C with several RCs in parallel.  The DA can make these unusable for sample and hold circuits because the instantaneous terminal voltage doesn't represent the true amount of charge inside the cap. 

If you suspect the cap you could replace it with a film cap just to test. DC leakage in the cap is another suspect but should be pretty small with everything biased and working near 0V. 

the behavior of the DC offset matches what I understand about the behavior of dielectric absorption, and maybe as Monte suggests the DC is then amplified 10x's creating the thump that lasts about 11ms (compared to the 20ms xfade).

It doesn't match what I understand about DA.

while muted how much AC voltage is present at node between two JFETS?

are gate voltages correct? For "muted" gate of Q6 should be 0V , gate of Q5 should be  minus several volts (J111 could require as much as 10V to fully pinch off). If Q5 doesn't turn fully off it could increase the Noise gain of U5B but that shouldn't automatically cause DC shift.

Something is converting AC to DC and it isn't DA in the input cap, primary suspects are the JFETs. If there is voltage swing at the source of Q5 and the gate voltage is marginal to cut off, that could modulate the on resistance of the JFET asymmetrically or differently for positive and negative audio signal swing.

Does it behave any better (less bad) if you increase the two 4k7 resistors to 10k or 20k?

You mentioned the original design used J112s, they require smaller pinch off voltages.

JR

 

[sahib]

...............................
The preview for one of Douglas Self's books shows most of his text about the mute block. The figure on page 417 shows the main circuit. The figure on page 419 shows the addition of C115 and R22 (as named on my schematic), and point 2 under "Dealing with the DC Conditions" on page 420 discusses them. Above the figure on 417 he also discusses overlap of the switching.

When I first built the block, I had not included C115 and R22. I had thumps all the time. After their addition, the thumps only occur on unmute, after a significant gain change happens while muted.

C115 somehow seems good to me but I don't understand what R22 is doing. I'm not yet fully understanding where the DC offset is coming from.

R22 is there to prevent thump.

Surprisingly the DC could be coming through the very thing that is supposed to stop it. C55.

I would speculate on your gain switch environment. Make sure that there is no DC on it and also it  is a make before break type.

Any  glitch created on the left hand side of C55  will appear in its right hand side (integration). On MUTE this will charge C115 through R128.

This charge will appear on the output of U5B through R22 and stay there for a period of time determined by the input impedance of the following stage.

If you did not UNMUTE within this period of time C115 will have discharged and on UNMUTE there will be no DC on the input of U5B.

But if you UNMUTE within this period of time then you'll have a much greater DC on the input of U5B.

This is probably why you get no thump after waiting for a few seconds.

 

[electronicpresskit]

If you suspect the cap you could replace it with a film cap just to test. DC leakage in the cap is another suspect but should be pretty small with everything biased and working near 0V. 

Changing C55 to a 100N polypropylene cap still produces a thump, but it never exceeds -14mv and the shape is smoother.

Putting the 33uF electrolytic back in I immediately get the same > -100mv thump I've been seeing.

Changing C55 to a 1uF metallized polypropylene cap results in no thump!

Changing C55 to a .1uF polyester cap results in no thump!

Changing C55 and C115 to a 4.7uF electrolytic (same model as 33uF) results in a thump but no greater than 25-30mv. Increasing R128 and R132 to 20k has no effect on the thump, but get's us back to a good cutoff frequency. The amount of time to get no thump is also reduced to one or two seconds.

This is the 33uF cap I'm using http://www.mouser.com/ds/2/315/ABA0000CE97-706659.pdf

Unfortunately I don't have any non-polar electrolytics  in the same size as a film cap, so it seems hard to know if cap size or dielectric is making the difference...until I get some more caps.

Or could there still be something else?

Can I ASSume that when you say gain, you mean level?

yes

When mute is active Q6 is conducting and Q5 is open?  Voltage on C115 should be same as output of U5B (is it?).

No, but with R22 there shouldn't it be different?

U5B pin 7 hovers around 2-3mv DC.

C115/R22 junction shows a smoothed version of the input signal at +/-5mv, hovering synchronously with U5b pin 7.

while muted how much AC voltage is present at node between two JFETS?

+/- 47mv

are gate voltages correct? For "muted" gate of Q6 should be 0V , gate of Q5 should be  minus several volts (J111 could require as much as 10V to fully pinch off). If Q5 doesn't turn fully off it could increase the Noise gain of U5B but that shouldn't automatically cause DC shift.

Pin 3 of Q5 is 7.5v, and U5D pin 14 is at 9.9v
Adding a 10k parallel to R119 gives us 9.475v at pin 3 of Q5 and no difference in the thump.

 

[JohnRoberts]

If you suspect the cap you could replace it with a film cap just to test. DC leakage in the cap is another suspect but should be pretty small with everything biased and working near 0V. 

Changing C55 to a 100N polypropylene cap still produces a thump, but it never exceeds -14mv and the shape is smoother.

Putting the 33uF electrolytic back in I immediately get the same > -100mv thump I've been seeing.

Changing C55 to a 1uF metallized polypropylene cap results in no thump!

Changing C55 to a .1uF polyester cap results in no thump!

I'd be suspicious that DC leakage current is a factor while the polypropylene should be very low leakage, like the other film caps.

I still don't suspect DA but there is a relationship between DA and changing or alternating termination impedance.  When muted or not, the input path should express very similar impedance, but transiently during switching between muted and un-muted, or back, both FETs can be open and high impedance. So I'll give DA a weak maybe.

Changing C55 and C115 to a 4.7uF electrolytic (same model as 33uF) results in a thump but no greater than 25-30mv. Increasing R128 and R132 to 20k has no effect on the thump, but get's us back to a good cutoff frequency. The amount of time to get no thump is also reduced to one or two seconds.

Smaller C55 could cause less leakage current and/or less DA. So I can't draw any conclusion other than moving in right direction. Making C115 smaller reduces time it takes to rebalance to op amp output voltage.

This is the 33uF cap I'm using http://www.mouser.com/ds/2/315/ABA0000CE97-706659.pdf

Leakage of blah blah + 3uA is not exactly low leakage, but i ASSume the pre-mute audio feed is nominally 0V dc.

Unfortunately I don't have any non-polar electrolytics  in the same size as a film cap, so it seems hard to know if cap size or dielectric is making the difference...until I get some more caps.

How strict is your self noise budget? Scaling up to 50-100k could allow much smaller C values.

Or could there still be something else?

Probably ... we're looking at the symptoms without complete understanding of cause.

Can I ASSume that when you say gain, you mean level?

yes

When mute is active Q6 is conducting and Q5 is open?  Voltage on C115 should be same as output of U5B (is it?).

No, but with R22 there shouldn't it be different?

that looks like the plan

U5B pin 7 hovers around 2-3mv DC.

+2mV to +3mV DC? or +2mV to -3mV

C115/R22 junction shows a smoothed version of the input signal at +/-5mv, hovering synchronously with U5b pin 7.

What does VOM read when probing directly across R22...?

while muted how much AC voltage is present at node between two JFETS?

+/- 47mv

are gate voltages correct? For "muted" gate of Q6 should be 0V , gate of Q5 should be  minus several volts (J111 could require as much as 10V to fully pinch off). If Q5 doesn't turn fully off it could increase the Noise gain of U5B but that shouldn't automatically cause DC shift.

Pin 3 of Q5 is 7.5v, and U5D pin 14 is at 9.9v
Adding a 10k parallel to R119 gives us 9.475v at pin 3 of Q5 and no difference in the thump.

-9.475?? Sounds close enough to -10V , while data sheet says -10v worse case, just for argument if it actually requires 10V and source  has 47mV of signal that could modulate it's "offness" (not a word).

It sounds like you are making progress...

Note, another minor tweak is instead of connection R70 to ground (0V) you could connect the 1M resistor to the output of u5B. This would charge the input cap up to the correct voltage for no thumps (maybe.... I really don't like to alter respected people's designs on public forums.)

He does publish his email address on his website while I don't know how enthusiastic he would be to participate.

JR

 

[electronicpresskit]

Leakage of blah blah + 3uA is not exactly low leakage, but i ASSume the pre-mute audio feed is nominally 0V dc.

yes, the pre-mute feed looks only slightly more noisy than GND.

How strict is your self noise budget? Scaling up to 50-100k could allow much smaller C values.

It’s a good suggestion. I stayed away from it because Self’s text says 4k7 is best for J112’s providing -120db of reduction, while 22k is only -110db. I ASSumed going to 50k or 100k would surely mean even less reduction. I did try it now though with 1uF metallized polypropylenes, and while I can’t discern any less gain reduction, the increased noise is pretty bad comparatively. I think I would choose the caveat of the wait 2 seconds before you unmute over the increased noise.

I should add that upon more careful examination of how long I have to wait to unmute before no thump, I find that I can get thumps up to -120mv if I unmute it quickly. That makes me think the dielectric defines the possible thump size and the cap size determines how quickly it discharges. The 1uF polypropylenes with 100k’s still had no thump.

U5B pin 7 hovers around 2-3mv DC.

+2mV to +3mV DC? or +2mV to -3mV

ah…I meant between +2mV and +3mV

What does VOM read when probing directly across R22...?

93.8k with power off

-9.475?? Sounds close enough to -10V , while data sheet says -10v worse case, just for argument if it actually requires 10V and source  has 47mV of signal that could modulate it's "offness" (not a word).

yeah, -9.75v

Note, another minor tweak is instead of connection R70 to ground (0V) you could connect the 1M resistor to the output of u5B. This would charge the input cap up to the correct voltage for no thumps (maybe.... I really don't like to alter respected people's designs on public forums.)

He does publish his email address on his website while I don't know how enthusiastic he would be to participate.

JR

R70 is not in the original circuit, I added that at the advice of a friend with the idea that it holds that node at 0v when there’s no signal passing through the cap.

I tried adding the 1M to U5B pin 7 and there’s no discernable difference in the behavior.

I wrote to Mr. Self a few days ago but haven’t heard anything back from him.

Thanks!

epk

 

[JohnRoberts]

Leakage of blah blah + 3uA is not exactly low leakage, but i ASSume the pre-mute audio feed is nominally 0V dc.

yes, the pre-mute feed looks only slightly more noisy than GND.

I am asking about the "V" namely DC volts as that will directly influence dc leakage current in a cap.

How strict is your self noise budget? Scaling up to 50-100k could allow much smaller C values.

It’s a good suggestion. I stayed away from it because Self’s text says 4k7 is best for J112’s providing -120db of reduction, while 22k is only -110db. I ASSumed going to 50k or 100k would surely mean even less reduction. I did try it now though with 1uF metallized polypropylenes, and while I can’t discern any less gain reduction, the increased noise is pretty bad comparatively. I think I would choose the caveat of the wait 2 seconds before you unmute over the increased noise.

The total attenuation of that mute is the product of pad formed by R125 and on resistance of Q6 through c115 to gnd "and" pad formed by off resistance of Q5 (probably also capacitance) divided by R132.  So higher R improves one and hurts the other. Too high R values will also suffer from capacitance coupled in between gate signal and channel, but the gates use RC to slow them down to reduce edge coupling. 

I should add that upon more careful examination of how long I have to wait to unmute before no thump, I find that I can get thumps up to -120mv if I unmute it quickly. That makes me think the dielectric defines the possible thump size and the cap size determines how quickly it discharges. The 1uF polypropylenes with 100k’s still had no thump.

U5B pin 7 hovers around 2-3mv DC.

+2mV to +3mV DC? or +2mV to -3mV

ah…I meant between +2mV and +3mV

What does VOM read when probing directly across R22...?

93.8k with power off

Sorry I meant the V of VOM, or what voltage is across the R22 while on  Should be 0V dc and probably is after settling . Since audio input is cap coupled if there is voltage drop across R22 where is that current coming from, or going.  What is stabilizing over time to not click... ?

-9.475?? Sounds close enough to -10V , while data sheet says -10v worse case, just for argument if it actually requires 10V and source  has 47mV of signal that could modulate it's "offness" (not a word).

yeah, -9.75v

Note, another minor tweak is instead of connection R70 to ground (0V) you could connect the 1M resistor to the output of u5B. This would charge the input cap up to the correct voltage for no thumps (maybe.... I really don't like to alter respected people's designs on public forums.)

He does publish his email address on his website while I don't know how enthusiastic he would be to participate.

JR

R70 is not in the original circuit, I added that at the advice of a friend with the idea that it holds that node at 0v when there’s no signal passing through the cap.

Maybe remove it, especially if it wasn't in the original design.  Pin 6 of U5B  will not likely be 0V (tl07x will typically have mV of DC offset voltage), so connecting a DC path to ground there will show up in the output voltage (albeit not very much V.. XmV x 4.7k/1M ) .  When the circuit is muted there is a DC path through R22, when un-muted there is a DC path through Q5, so it shouldn't be needed or help.

I tried adding the 1M to U5B pin 7 and there’s no discernable difference in the behavior.

If we're still talking about R70 I'd remove it..

Were any other parts added or modified, besides using the different JFETs?

I wrote to Mr. Self a few days ago but haven’t heard anything back from him.

Thanks!

epk

I was kind of kidding... but good luck.

JR

 

[electronicpresskit]

Leakage of blah blah + 3uA is not exactly low leakage, but i ASSume the pre-mute audio feed is nominally 0V dc.

yes, the pre-mute feed looks only slightly more noisy than GND.

I am asking about the "V" namely DC volts as that will directly influence dc leakage current in a cap.

The attached screenshot is what I see at pre-mute. It's the same as what I see when I look at GND except GND doesn't have the pulsewave on it.

Sorry I meant the V of VOM, or what voltage is across the R22 while on  Should be 0V dc and probably is after settling . Since audio input is cap coupled if there is voltage drop across R22 where is that current coming from, or going.  What is stabilizing over time to not click... ?

Correct, it reads 0V when stabil.
on unmute I see it go as low as -.0025v and then stabilize again at 0V. this is with both caps at 33uF and 20k for R128 and R132.

I tried adding the 1M to U5B pin 7 and there’s no discernable difference in the behavior.

If we're still talking about R70 I'd remove it..

yep, I removed R70 and it made no difference. Then I tried connecting it to U5B pin 7 and it made no difference so I removed it.

Were any other parts added or modified, besides using the different JFETs?

On the original:
The AC coupling caps are 47uF
The switching is driven by CMOS logic
A 10M resistor was parallel to D26 to accomplish slight positive bias of Q5 when conducting
R136 was 680k
R70 was not on the original

Thanks!

epk

 

[JohnRoberts]

Leakage of blah blah + 3uA is not exactly low leakage, but i ASSume the pre-mute audio feed is nominally 0V dc.

yes, the pre-mute feed looks only slightly more noisy than GND.

I am asking about the "V" namely DC volts as that will directly influence dc leakage current in a cap.

The attached screenshot is what I see at pre-mute. It's the same as what I see when I look at GND except GND doesn't have the pulsewave on it.

Thanx.. low enough DC that cap leakage current should be minimal.

Sorry I meant the V of VOM, or what voltage is across the R22 while on  Should be 0V dc and probably is after settling . Since audio input is cap coupled if there is voltage drop across R22 where is that current coming from, or going.  What is stabilizing over time to not click... ?

Correct, it reads 0V when stabil.
on unmute I see it go as low as -.0025v and then stabilize again at 0V. this is with both caps at 33uF and 20k for R128 and R132.

which supports that there is a DC voltage shift during mute.

I tried adding the 1M to U5B pin 7 and there’s no discernable difference in the behavior.

If we're still talking about R70 I'd remove it..

yep, I removed R70 and it made no difference. Then I tried connecting it to U5B pin 7 and it made no difference so I removed it.

good it wasn't doing anything useful and perhaps causing an input DC.

Were any other parts added or modified, besides using the different JFETs?

On the original:
The AC coupling caps are 47uF

shouldn't make a difference

The switching is driven by CMOS logic

shouldn't make a difference ASSuming similar Rs and C after the logic.

A 10M resistor was parallel to D26 to accomplish slight positive bias of Q5 when conducting

a slight positive gate voltage will reduce JFET on resistance.... but, if this gate voltage is high enough for the gate diode to start conducting that gate diode current will flow into the drain-source channel , and in this case into the - input of U5B.  The on resistance of Q5 should be low wrt R128 while error would be slight drop from unity gain and perhaps distortion (but not thumps).

R136 was 680k

we have touched on this before.. 

Revisiting the gate drive voltage J111 requires as much as 10V to fully pinch off.  The left side of the schematic is cut off, so I will ASSume U5D output saturates rail to rail (for 12V supply and TL074, 11V and change). U5C with the help of R137 should saturate negative (-11V and change ?).  The voltage divider formed by R134 and R136 will never pull the gate of Q6 to -10V even with original values (recall that J112 works with smaller pinch off voltages).  If Q6 does not fully turn off when muted it would cause even more mischief than thumps, but 300k makes this worse wrt attaining the 10V gate voltage spec. 

R70 was not on the original

Thanks!

epk

I would get the Q6 gate voltage more negative just on general principles. I guess this could explain different DC operation points between mutes and un-muted. (speculation). 

If a circuit design does not meet worst case data sheet criteria you will often get bit by that at some later point in large scale production.

Good luck..

JR

 

[electronicpresskit]

Holy ****, the solution to this is way too obvious...

Changing R22 to 4k7 solves the problem completely. This must be a typo on the original schematic. I had wondered why 47k was the value there and couldn't ever make sense of it.

Thank you so much for your patience and continued efforts John Roberts! and thank you to everyone else who gave this some thought!

Cheers!

epk

 

[clintrubber]

Holy sh*t, the solution to this is way too obvious...

Changing R22 to 4k7 solves the problem completely. This must be a typo on the original schematic. I had wondered why 47k was the value there and couldn't ever make sense of it.

Nice find! On his website, Douglas Self lists errata of his books.

http://www.douglas-self.com/ampins/books/errata-ssad2.htm

If you happen to read this you might want to consider notifying him, and hear what his take is on it.

Bye

 

[Bo Deadly]

If you happen to read this you might want to consider notifying him, and hear what his take is on it.

I don't think it's a typo. That 47K is just to provide a DC feedback path. The value should not be terribly important.

If I had to guess I would be more suspicious of this (regarding 10M Rp across reverse bias diode):

it's a high value R used to slightly positively bias the jfet above 0v to reduce on resistance. it's not applicable here as my control circuit switches between 0v and -10v instead of +/- 7.5v as Douglas Self's example (with J112) is originally.

If the control voltages are not symmetric, that might cause offset issues.

Also, the series JFET needs a little positive voltage on the gate so that it's super ON or you will get more distortion.

 

[clintrubber]

I don't think it's a typo. That 47K is just to provide a DC feedback path. The value should not be terribly important.

I agree, I was surprised this value-change did the trick, but it may also have been a lucky tweak for the specific layout/circuit at hand, so not be a generally valid solution. Who knows  it all falls into place when we draw the various paths the charges dance around here in this topology.

Note though/FWIW that the version of this circuit in one of the other Self books (SSAD 2nd ed) uses 47k & 47uF here,  not 33uF . But as said, FWIW, ... if timing is critical w.r.t. eventual cancellations and whatnot, one shouldn't use blindly grabbed electrolytics

If I had to guess I would be more suspicious of this (regarding 10M Rp across reverse bias diode):
If the control voltages are not symmetric, that might cause offset issues.

Also, the series JFET needs a little positive voltage on the gate so that it's super ON or you will get more distortion.

As Self described, the Rp is added exactly for that reason: push the series-JFET a bit more (add 300mV max) for lowered Rds(on)


Bye

 

[clintrubber]

Some more:

* Switching by -10/0 iso +/-7.5  AND  replacing J112 by J111 sounds like two steps into the wrong direction ?!  (This thread might have already addressed that)

* The first (and only?) schematic in this thread suggest the symmetry of the switching voltages around the mid-supply opamp-reference is violated?

* Who knows the TL074 doesn't provide the same symmetry w.r.t. max/min values as a CMOS gate?
(  http://www.ti.com/ds_dgm/images/fbd_slos080n.gif  )
If say amount of charge injection needs to be balanced out, then more potential contributors/component-values may need to be addressed, which doesn't seem a likely approach. At least I assume this circuit to be meant as an assemble-it-in-a-carefully-designed-layout, but no need for component selection


Bye

 

[clintrubber]

... this message corrected by deleting all previous text 

 

[abbey road d enfer]

For example, I input a +/-1.6v triangle wave

Why a triangle wave? Why not a good ole sinewave? Triangle can be assymetrical, which could result in rectification, changing the DC op point.

 

[JohnRoberts]

dead thread walking...

JR

 

[abbey road d enfer]

dead thread walking...

JR

Ah! Ah!
I swore I wouldn't get fooled again...