Turnstile Audio TAC700 schematic

[DFischer]

I've previously posted a schematic on the Turnstile Audio TAC1100 mic in THIS thread. Out of curiosity, I also bought a pair of Turnstile TAC700 mics and decided to do the same. Being a cheap transformerless mic, I was expecting it might use a Schoeps circuit, but it appears to be an impedance balanced output instead. Here's what I have so far. Any comments are welcome. I'm learning a lot by doing this, and hopefully the schematics are useful to somebody.

 

[DFischer]

A couple of questions:

1. The circuit looks flat to my inexperienced eyes. Am I correct?
2. I tried to figure out what kind of oscillator was used so that I could draw Q1 more accurately. The two inductors made me think it might be a Hartley oscillator, but that doesn't seem to fit. I noticed it was almost identical to the one used in Studio Projects C1. However, the output to the voltage quadrupler is taken at a different node. Would this still be correct? What is this oscillator circuit called?

C1 Oscillator


TAC700 oscillator???

 

[Khron]

The circuit looks flat to my inexperienced eyes. Am I correct?

If by "flat" you mean "with no high-frequency attenuation", then yeah, it's flat.

I'm still not 1000000% convinced about the accuracy of that schematic, though...

 

[micolas]

@DFischer
Check carefully if you have drawn the diagram correctly.

 

[DFischer]

@DFischer
Check carefully if you have drawn the diagram correctly.

Will do, thanks!

 

[micolas]

@DFischer
About DC/DC converter:
You can collect and rectify/multiply the high frequency voltage produced by the oscillator, either against GND or against U+.

 

[RuudNL]

I suppose in the C1 schematic C12 is connected to the 'left' side of L2, not to the base of the transistor.

 

[Voyager10]

The circuit around R9/R10/R11 would be easier to read if it were redrawn to show 'pin 4' as the positive supply rail (at the top, therefore). R10/R11 are then a simple voltage divider which biases the JFET gate to half the supply voltage via R9. Q2 is a simple source follower, with the drain going straight to the +ve supply.

It might also help to redraw the pattern-select switch, to use ground instead of 'pin 1' (the same thing, just confusing).

The unusual thing about this circuit is putting the pad after the JFET stage, so if that stage is overloading, the pad won't do anything to help.

 

[micolas]

The circuit around R9/R10/R11 would be easier to read if it were redrawn to show 'pin 4' as the positive supply rail (at the top, therefore). R10/R11 are then a simple voltage divider which biases the JFET gate to half the supply voltage via R9. Q2 is a simple source follower, with the drain going straight to the +ve supply.

It might also help to redraw the pattern-select switch, to use ground instead of 'pin 1' (the same thing, just confusing).

The unusual thing about this circuit is putting the pad after the JFET stage, so if that stage is overloading, the pad won't do anything to help.

A scheme must be drawn in such a way that it has an electronic, functional logic, as simple as possible.

 

[pderbidge]

Does anyone know what governs the low end in this type of circuit/schematic?

 

[Khron]

Does anyone know what governs the low end in this type of circuit/schematic?

C12 & C13