8 channel AD converter idea/discussion

[jdbakker]

[quote author="Michael Krusch"]I read the Wavefront document about 96k over ADAT (http://www.wavefrontsemi.com/UserFiles/File/AL_Info/ADATOptical96KAddendum1.0.pdf). Is this something the converter chips are supporting or do I need an additional processor to scramble the data? Then a 96k converter with ADATA interface will be more complex.[/quote]
Indeed.

For S/MUX, you need to build a multitap digital delay line, which takes a lot of registers. So either have a few dozen HCMOS chips (large, noisy), one or a few CPLDs (less noisy, more complex) or a microcontroller or DSP (even more complex). Wavefront have an appnote for their AL3101 "DSP" to do S/MUX.

For a simple DIY analog-to-ADAT box you may want to stick to 24/48k.

JDB.
[I'd rather have a very good 24/48 ADC than a noisy 24/96 one]

 

[TobWen]

I didn't draw all the parts and connections, since I don't have software on this computer. So don't laugh, I had to use a demo-version of sPlan

In my opinion, this should be a low-jitter solution for the ADC and ADAT-OptoGen. Simple and effective.

I've also designed a high-quality input-buffer, which I will share for DIY in the next days (have to finish some exames).

This is for 44.1 kHz, since I don't work in other frequencies.
Of course, you can hook up another TENT-clock for 48 kHz and switch between them.

It wasn't possible to use 22.5792 MHz and MDIV (high), since TENT doesn't have these XOs :-((

JDB - what do you think?

 

[jdbakker]

Have you checked all setup/hold times ?

For best noise performance, you want the CS53x1's VD and VL to be 3.3V. This does mean that you need voltage translators between it and the ADAT TX. Similarly, for best noise performance you want the CS53x1 to be clock slave not master.

JDB.

 

[TobWen]

[quote author="jdbakker"]Have you checked all setup/hold times ?[/quote]

No, but it should work this way. Where do you see problems?

[quote author="jdbakker"]For best noise performance, you want the CS53x1's VD and VL to be 3.3V. This does mean that you need voltage translators between it and the ADAT TX.[/quote]

You're right ... page 4 of the Cirrus-datasheet

ADAT-TX says min 0,75 VDD on inputs.
But I need to run the Cirrus on 3.3V digital and the ADAT on 5V?

[quote author="jdbakker"]Similarly, for best noise performance you want the CS53x1 to be clock slave not master.[/quote]

But then, LRCK is an input ... do I have to clock the ADAT-TX with TENT directly?
On what speed / MHz?

 

[jdbakker]

[quote author="TobWen"][quote author="jdbakker"]Have you checked all setup/hold times ?[/quote]
No, but it should work this way.[/quote]
How do you know 'it should work this way' if you haven't checked? With digital interconnects, you should always check setup/hold/propagation times vs clock speed.

[quote author="TobWen"][quote author="jdbakker"]For best noise performance, you want the CS53x1's VD and VL to be 3.3V. This does mean that you need voltage translators between it and the ADAT TX.[/quote]
You're right ... page 4 of the Cirrus-datasheet

ADAT-TX says min 0,75 VDD on inputs.
But I need to run the Cirrus on 3.3V digital and the ADAT on 5V?[/quote]
Yes.

[quote author="TobWen"][quote author="jdbakker"]Similarly, for best noise performance you want the CS53x1 to be clock slave not master.[/quote]
But then, LRCK is an input ... do I have to clock the ADAT-TX with TENT directly?
On what speed / MHz?[/quote]
That's in the converter datasheet.

Tob, don't get me wrong, but these are very basic digital interfacing design issues. Are you sure you're up to a design like this?

JDB.

 

[TobWen]

[quote author="jdbakker"]How do you know 'it should work this way' if you haven't checked? With digital interconnects, you should always check setup/hold/propagation times vs clock speed.[/quote]

Since I'm not the first one, who's using a CS53x1 with ADAT-TX

[quote author="jdbakker"]That's in the converter datasheet.[/quote]
You might be right, but I'm not as experiences as you.

[quote author="jdbakker"]Tob, don't get me wrong, but these are very basic digital interfacing design issues. Are you sure you're up to a design like this?[/quote]

You're completly right ... since I'm doing DIY for hobby only, I'm not very experienced with this basic digital stuff.

But since we're on page 8, complaining about a good 8-channel-AD, it's time to start doing it

I've created a very nice input-buffer, since I've pretty much experience with the analog-part right now. I want to fix the digital part now.

 

[mhelin]

[quote author="Rochey"]
I'm toying with the idea of an 8 channel AD converter for use with one of those behringer control surfaces with ADAT i/O.
[/quote]

I've been lately toying with the idea of an 8 ch AD for use with any digital (S/PDIF AES/EBU) audio interface which support the 129 kHz sample rate. I've got the Freescale Soundbite DSP kit but don't know if it supports 48 kHz sample rate on the A/D's and the required 192 kHz on the digital ports simultaneusly. Because 192 (khz) = 4x 48 (khz) you could stuff 4 stereo (=8 mono) channels of 22 bit data (for ~ 132 dB dynamic range) into that format with the 192 kHz sample rate if you sacrifaced the 2 LSB's for the channel number 0 - 3 (maybe it would be enough to use single bit to mark the frame begin, also you could use a bit or two for MIDI as well like to control the DSP parameters). There are no drivers which support that kind of multichannel S/PDIF (de/multiplexing, "converting" sample rates etc.) though, but you could do simple 8 ch recording with any audio program but would need to decode the data from 8 ch WAV files yourself. Well, in Linux developing some Jack plugin would be propably easier than writing some Windows drivers.

 

[TobWen]

@JDB:
for using the CS5x61 in slave-mode, I need to do this:

- generate 11.2896MHz to feed MCLK
- generate 2.8224MHz to feed SCLK
- generate 44.1kHz to feed LRCK
- set M1 and M0 to 0
- set I2S/!LJ to 0

So I need various XOs or a counter/divider ...
Should I use normal 74xx for this? What do you think?

 

[jdbakker]

[quote author="TobWen"][quote author="jdbakker"]How do you know 'it should work this way' if you haven't checked? With digital interconnects, you should always check setup/hold/propagation times vs clock speed.[/quote]
Since I'm not the first one, who's using a CS53x1 with ADAT-TX [/quote]
Probably not. Are you sure those other designs have no additional logic or registers between the CS53x1 and the ADAT-TX? This will affect the timing.

[quote author="TobWen"]I've created a very nice input-buffer, since I've pretty much experience with the analog-part right now. I want to fix the digital part now.[/quote]
The problem with digital stuff (especially with >10MHz clocks) is that it is all too easy to make a design which almost works, or which works most of the time. The problem with mixed-signal designs is that it is very easy to get unwanted coupling between digital and analog sections, which invariably raises the noise floor higher than you'd like. Plenty of commercial products show similar flaws, and these things are harder to debug than analog designs, as they require specialized test equipment. Not trying to discourage you or anything (it's your time and money after all), just suggesting that you are very careful in checking everything and don't assume that things will work just because others have similar designs working.

[quote author="TobWen"]@JDB:
for using the CS5x61 in slave-mode, I need to do this:

- generate 11.2896MHz to feed MCLK
- generate 2.8224MHz to feed SCLK
- generate 44.1kHz to feed LRCK
- set M1 and M0 to 0
- set I2S/!LJ to 0
[/quote]
Looks OK.

[quote author="TobWen"]So I need various XOs or a counter/divider ...
Should I use normal 74xx for this? What do you think?[/quote]
What's 'normal' 74xx ?

For dividers and logic I would suggest either 74HC or 74AHC. Always take the slowest logic family which will still support your maximum speed; extra speed will only increase EMI/RFI. Pick synchronous dividers over asynchronous ones for noise reasons, and/or reclock the divider's output with an additional D flipflop (such as 74xx374). Provide plenty of decoupling. Do not use 74AC series logic, as it's very noisy.

Guido Tent has written more about all of this. If you have access to a large (academic) library I suggest you read Howard Johnson's "High Speed Digital Design: A Handbook of Black Magic". Dr. Johnson has several publications on digital interconnects on http://www.sigcon.com/ ; worth checking out.

JDB.
[and try to avoid broad generalizations, too]

 

[TobWen]

[quote author="jdbakker"]Probably not. Are you sure those other designs have no additional logic or registers between the CS53x1 and the ADAT-TX? This will affect the timing.[/quote]

Not according to the datasheets. There's about 115ns leeway between the output time of the CS5361 and the setup time of the AL1401AG, and 147ns between the hold time of the AL1401AG and the next output of the CS5361. Should be okay?

 

[TobWen]

[quote author="jdbakker"]For dividers and logic I would suggest either 74HC or 74AHC. Always take the slowest logic family which will still support your maximum speed; extra speed will only increase EMI/RFI. Pick synchronous dividers over asynchronous ones for noise reasons, and/or reclock the divider's output with an additional D flipflop (such as 74xx374). Provide plenty of decoupling. Do not use 74AC series logic, as it's very noisy.[/quote]

Okay, so I should go for two 74HC192 (synchronous 4-bit-counters).
When I cascade them, I'll get a synchronous 8-bit-counter.
The 8-bit-counter can divide through 4 and through 256:

Tent-XO with 11.2896 MHz / 4 = 2.8224 MHz or / 256 = 44.1 kHz.

What do you think?

 

[playboss]

http://www.analog.com/en/prod/0,2877,AD9511,00.html

 

[Andy Peters]

[quote author="playboss"]http://www.analog.com/en/prod/0,2877,AD9511,00.html[/quote]

Can you clock that slow enough to work with I2S signals?

-a

 

[playboss]

sure. look for "clock distribution" thread at diyaudio.com

 

[TobWen]

[quote author="playboss"]sure. look for "clock distribution" thread at diyaudio.com[/quote]

Could you please be more detailed? You can PM me a link, if you want.
There are hundrets of topics with that title

About AD9511:
I don't need 1.2 GHz Clock ... so some fast SMD-logics should be fine?

 

[playboss]

http://www.diyaudio.com/forums/showthread.php?s=&threadid=54023


personally, I think you should buy some PCM4222 Ev kits , swap some IC-s and build nice PSU , VU meters

 

[TobWen]

[quote author="playboss"]http://www.diyaudio.com/forums/showthread.php?s=&threadid=54023


personally, I think you should buy some PCM4222 Ev kits , swap some IC-s and build nice PSU , VU meters [/quote]

In my opinion, this is about reclocking a data-stream for a DAC.
This thread is about ADC

Isn't such a "big" chip, like the AD9511 producing more jitter than some ultra-fast logic-parts?

 

[playboss]

http://focus.ti.com/docs/toolsw/folders/print/pcm4204evm.html

just read the topic, it makes no difference whether you clocking _locally_ ADC or DAC.
Jitter spec is the neatest about the 9511 :razz:

 

[TobWen]

Without using AD9511, is this design okay? It's asynchron, I think.

 

[playboss]

well i tought this topic is about 8 channels of ad conversion . I dont have experience about adat format. TI use LVC logic - perhaps check EV-kit schematics.

how old news is this ? - http://www.wavefrontsemi.com/dice2A.html