> there is no direct discharge path for the cap other than the gate of the FET, I'm assuming the existing values probably result in a very long release time.
> no idea how to model release time
"model release time".... if you had a simple circuit, you would use a SPICE pulse (or switch) to apply a voltage, then wait (forever, or until math-error accumulates) for it to decay. And a perfect diode to a cap, NO other path, would take forever to decay (in real life, it may actualy drift "UP").
HOWever... in your plan, if you assume a voltage on C62, where can it go? Through R86 to R55 to a bunch of voltages "following the signal". As abbey road d enfer says more concisely.
I would have real doubt about any sidechain numbered up to C62. Rule-of-thumb: when I take off my socks to keep track of what-does-what, it is too complicated for me, and perhaps too complicated to be doing what I want to do.
I would have strong doubt about any scheme with "no ...discharge path for the cap". If true, the cap can never decay. In a real world, stray leakage will drift the cap voltage to ANY voltage, including unhappy zones. Now, if there is a RESET button, my doubt is weaker; still I'd think about something to drain leakage, how large that leakage could be, why I would want to hold a voltage for very long time, if this may be a chore for a PIC/STAMP (digital can hold until the lights go out).
> no idea how to model release time
"model release time".... if you had a simple circuit, you would use a SPICE pulse (or switch) to apply a voltage, then wait (forever, or until math-error accumulates) for it to decay. And a perfect diode to a cap, NO other path, would take forever to decay (in real life, it may actualy drift "UP").
HOWever... in your plan, if you assume a voltage on C62, where can it go? Through R86 to R55 to a bunch of voltages "following the signal". As abbey road d enfer says more concisely.
I would have real doubt about any sidechain numbered up to C62. Rule-of-thumb: when I take off my socks to keep track of what-does-what, it is too complicated for me, and perhaps too complicated to be doing what I want to do.
I would have strong doubt about any scheme with "no ...discharge path for the cap". If true, the cap can never decay. In a real world, stray leakage will drift the cap voltage to ANY voltage, including unhappy zones. Now, if there is a RESET button, my doubt is weaker; still I'd think about something to drain leakage, how large that leakage could be, why I would want to hold a voltage for very long time, if this may be a chore for a PIC/STAMP (digital can hold until the lights go out).