Comparison of JFETs for mic applications

[rogs]

I've been using an OPA1641 in a very similar circuit with my OPIC project for the last couple of years now....
Low distortion, decent headroom and a reasonably low noise figure.
No more deciding on whether to go for low distortion or symmetrical clipping, as you need to do with discrete FET inputs...
The noise level maybe slightly higher than some JFET input circuits, but I've never found it to be a problem.....

 

[Matador]

Here's the circuit

Is it just me or is C5 backwards?

 

[rogs]

Is it just me or is C5 backwards?

No, it's the right way in this configuration...... The +ve end has the full phantom power voltage applied, whereas the -ve side only has the lower op-amp output voltage applied.
The output is biased at the same potential as the non-inverting input, the 'half rail' value derived from the junction of R4 and R5, and applied via R2 and R3

 

[Matador]

Of course...duh!

 

[Somkereki]

OPA1641 Initial Results​

Here's the circuit - just a very simple voltage follower running off P48 power:

View attachment 128224
R6 can be chosen to set the supply voltage, in this case 24V. Supply current is approximately 1.7mA, and there's 41.6V available at XLR pins 2 and 3 for capsule polarisation.

Measurements (all at 1KHz) are as follows:

Value	Cin=1nF	Cin=68pF
Voltage gain (100mV in)	-0.3dB (x0.96)	-1.2dB (x0.87)
Input noise, A-weighted	-122.9 dBV	-119.4 dBV
THD, 100mV RMS in	0.00052%	0.00057%
THD, 500mV RMS in	0.00047%	0.00040%

Caveats​

• The construction might be responsible for some excess input capacitance (I used the IC soldered to a carrier board, plugged into an IC socket, soldered to a perfboard), which lowers the voltage gain (and raises the input noise) for Cin=68pF. I may try an 'air-wired' build.
• A practical microphone circuit would probably use a second high-value resistor at the input, which would increase the low-frequency noise.
• THD numbers really just mean "lower than I can measure" here. See the spectrum below - most of what you're seeing is the signal source (an iPhone!) rather than the amp itself. View attachment 128230

The noise curves look like this - again, it's possible that lowering the input capacitance might bring the green one down by a fraction.

View attachment 128231

Nowadays, it is worth examining the 1/f noise even under a frequency of 20 Hz! Because everything will be digitized in the end. Few people know the effect when high level 1/f noise "phase modulates" the harmonics belonging to the fundamental tone, which causes an unnatural sound. I noticed this a long time ago, in the analog era, although my colleagues told me not to worry about it, our ears can't hear below 20 Hz anyway.

 

[k brown]

Nowadays, it is worth examining the 1/f noise even under a frequency of 20 Hz! Because everything will be digitized in the end. Few people know the effect when high level 1/f noise "phase modulates" the harmonics belonging to the fundamental tone, which causes an unnatural sound. I noticed this a long time ago, in the analog era, although my colleagues told me not to worry about it, our ears can't hear below 20 Hz anyway.

Doesn't need to be done in the microphone, though. Just high pass it somewhere down the line.

Many decades of successful recordings made with mics that don't have infrasonic filtering in them.

 

[Voyager10]

TL071 comparison​

Purely for fun, I put a TL071 into the previous circuit and measured it:

Value​	Cin= 1nF​	Cin = 68pF​
Gain	-0.3dB	-1.2dB
Input Noise, A-weighted	-112.6 dBV	-111.2 dBV
THD, 100mV in	0.00082%	0.0062%
THD, 500mV in	0.0024%	0.031%

Here's the input noise comparison:


and the spectrum for that 500mV / 68pF THD figure looks like this:

 

[Voyager10]

"Schoeps" circuit measurements​

I've made some measurements of different FETs in the "Schoeps circuit", used in various forms in the Schoeps CMC series, MXL 603, 440, 770, 990, Takstar CM60/CM63, the (original) Alice microphone, and many other transformerless mics.

The schematic I'm using is as follows:


It was built on a PCB from Robert Jenkins' website, adapted to allow the FET to be pluggable, and the source capacitance to be selectable. Here it is in the box:

 

[Voyager10]

Summary data​

The same set of devices from previous tests were used. I omitted the J201 FET, as its Idss is too low to allow consistent biasing.

For each device:

• Trimmer R17 was adjusted to give 2.85V across R16, corresponding to 1.3mA drain current. This means the drain and source are at 1/4 and 3/4 of the supply rail, respectively.
• The Vgs column is the measured gate-source voltage for 1.3mA bias.
• The Gainmeasurement shows the differential output voltage for a given input (measured at 1KHz, 100mV RMS input). There are two measurements, for 1nF and 68pF input capacitance.
  • The '1nF' figure primarily reflects the FET's transconductance, the higher the transconductance the closer it gets to an ideal gain of 2.
  • The '68pF' figure shows the effect of FET gate-source and drain-gate capacitance for a typical LDC capsule. Lower capacitance means the gain is closer to the 1nF figure.
• THD is the overall figure reported by REW for a 1KHz, 100mV RMS input signal, again with 1nF and 68pF source capacitance. This corresponds to an SPL of 114dB for a typical capsule with 10mV @ 1Pa sensitivity.
• Ein is the equivalent input noise (in other words, the output noise divided by the gain), A-weighted. Again, measured with 1nF and 68pF source capacitance.

Device	Vgs @ 1.3ma	Gain @ 1nF	THD, 1nF (%)	Ein, 1nF (dBV-A)	Gain @ 68pF	THD, 68pF (%)	Ein, 68pF (dBV-A)
2N3819	-2.28​	1.63​	0.033​	-123.5​	1.52​	0.026​	-120.3​
2SK117-BL	-0.29​	1.86​	0.0077​	-123.6​	1.66​	0.0077​	-120.3​
2SK118-GR	-0.92​	1.6​	0.061​	-123.2​	1.44​	0.04​	-120.1​
2SK170-BL ii	-0.30​	1.89​	0.01​	-124.2​	1.52​	0.043​	-120.6​
2SK208-GR	-0.80​	1.62​	0.058​	-123.3​	1.45​	0.035​	-120.1​
2SK209-GR	-0.31​	1.88​	0.02​	-124.3​	1.59​	0.016​	-120.5​
2SK30A-GR	-0.92​	1.56​	0.064​	-122.9​	1.44​	0.052​	-120.0​
2SK880-GR	-0.28​	1.88​	0.016​	-124.3​	1.6​	0.017​	-120.8​
2SK932-23	-0.41​	1.9​	0.009​	-124.3​	1.71​	0.011​	-120.7​
BF244B	-2.19​	1.64​	0.04​	-123.2​	1.53​	0.033​	-120.2​
J112	-2.48​	1.81​	0.008​	-124.1​	1.62​	0.01​	-120.5​
J113	-1.68​	1.83​	0.014​	-124.1​	1.63​	0.0071​	-120.6​
J305	-1.28​	1.65​	0.02​	-123.4​	1.54​	0.015​	-120.4​

I've also attached REW's noise plots for the various FETs overlaid. They are all remarkably similar - a little bit of simulation suggests that the LF end is determined by the source capacitance and 1G resistor R18 (see earlier posts), and at the HF end it's largely generated by 2K2 resistor R10; the FET noise itself isn't making much difference.

 

[Voyager10]

Bias settings​

I was wondering how critical the bias was for best performance - several cheaper mics have fixed resistors instead of R17.

Here's a preview of the next set of measurements:

The idea here is to set a bias (drain) current, then gradually increase the input level until REW is reading 0.5% THD. The chart then compares different FETs with different bias currents.

This needs a lot of measurements, so might be a while before it's complete.

 

[abbey road d enfer]

Summary data​

the FET noise itself isn't making much difference.

Have you found these noise measurements coherent with subjective evaluation?
Numbers seem to indicatte a very small difference and domination of KTC noise, but there may be differences in perceived noise...

 

[Voyager10]

Have you found these noise measurements coherent with subjective evaluation?

Yes. I can't say I've auditioned each FET's noise output, but when listening periodically to check for interference or hum it's always sounded like clean white noise (if that's a thing).

I've not heard any popcorn noise in the FETs I'm testing, and I'm pretty sure that would show up in the spectrum analyser. It certainly shows up 50Hz hum at levels which are masked by the noise when listening.

 

[Voyager10]

Bias settings, full measurements​

For each of the FETs, using the circuit from post #48, I set the bias current (via R17) to a range of different values (measured with a DMM across R16). The circuit's input was connected to a signal generator, the output to a preamp/soundcard monitored by REW's RTA screen. Input capacitor was 68pF for all measurements.

For each FET + bias settings:
- using a signal generator, apply a known voltage level (0.36V RMS) to the input
- calibrate REW to the known level. (This means REW is showing the input signal level, accounting for the varying gain of the DUT).
- click the 'show distortion' button, adjust the signal generator output level up or down until REW reads 0.50% THD.
- record voltage level read by REW.

The drain current settings chosen were 0.3, 0.55, 0.8, 1, 1.25, 1.5 and 1.75mA. Not all FETs would allow the lowest currents, so there is no reading for some combinations. I didn't go about 1.75mA; all FETs showed a less-than-optimum max signal level by this point.

All voltages in the table below are RMS values. By my calculations, 1.8V RMS input corresponds to 139dB SPL for a capsule with a 10mV/Pa sensitivity figure.

Group 1​

Id (mA)	2SK209	2SK880	2SK170	2SK117	2SK932
0.3​	0.2​	0.2​	0.19​	0.19​
0.55​	0.58​	0.58​	0.65​	0.55​	0.55​
0.8​	1.19​	1.2​	1.39​	1.15​	1.46​
1​	1.82​	1.82​	1.87​	1.77​	1.8​
1.25​	1.83​	1.81​	1.27​	1.89​	1.56​
1.5​	1.28​	1.25​	0.77​	1.5​	1.27​
1.75​	0.72​	0.74​	0.48​	0.88​	0.79​

Group 2​

Id (mA)	J113	2N3819	J112	J305
0.3​	-	-	-	-
0.55​	-	-	-	-
0.8​	0.94​	-	-	0.6​
1​	1.47​	0.93​	-	0.94​
1.25​	1.85​	1.52​	1.81​	1.78​
1.5​	1.27​	1.29​	1.18​	1.23​
1.75​	0.65​	0.51​	0.59​	0.48​

Group 3​

Id (mA)	2SK208	2SK118	2SK30A	BF244B
Id (mA)	2SK208	2SK118	2SK30A	BF244B
0.3​	-	-	-	-
0.55​	0.26​	-	-	-
0.8​	0.47​	0.44​	0.36​
1​	0.68​	0.64​	0.51​	0.75​
1.25​	1.22​	1.1​	0.87​	1.25​
1.5​	1.36​	1.32​	1.32​	1.3​
1.75​	0.6​	0.55​	0.53​	0.53​

 

[Voyager10]

ORS87 results​

As I like measuring stuff, I've built an "ORS87" testbench (originally in this thread) using the ORS87Plus PCB (here) designed by @Khron .

Initial measurements are without the feedback / frequency shaping network, for simplicity. Looks like this:



The circuit was run off a bench power supply (48V in series with 8k2, connected to S1-/S2+) and the output was taken from P+ (via an OPA1641 buffer, see earlier posts) to a mic input.

Input was connected to BP, via a 68pF capacitor. The FET Q1 and feedback cap C4 were socketed. D1 is 33V and R7 is 20K, as per the ORS87-Plus BOM.


There are lots of things to play with here, so let's start with C4 and biasing:

Open-loop gain​

Using the J113 FET, the chart below show the gain for a variety of drain currents (Id) and choices for C4:




The drain current is set by adjusting trimmer R7. It also sets the drain voltage Vd of the FET. We have Id = (V_D1 - Vd) / 57K, where V_D1 is the Zener voltage. In my build the zener measured as 33.6V, so we got the following:

Vd (V)	Id (mA)
22.2	0.20
19.4	0.25
16.5	0.30
13.7	0.35
10.8	0.40
8.0	0.45
5.1	0.50

Distortion​

Two charts here. The first shows distortion varying with Id, for a fixed input level (100mV RMS at 1KHz).



The second shows distortion varying with input signal level, when Id is tuned for lowest distortion at 100mV.

Opinions​

• Running without C4 isn't really an option, THD is very high without it, and it's asking a lot of the frequency-shaping network to provide corrective negative feedback. The network doesn't provide much feedback except at frequency extremes. I'll measure this later.
• The gain appears to be almost entirely dependent on the capacitances in the circuit, rather than the FET transconductance (which varies with Id, but is independent of C4).
• C4 = 10pF is probably OK for a 4:1 output transformer, and 5pF for a 7:1 or higher transformer, assuming you want around unity gain from capsule to mic output.
• Biasing is important but not super-sensitive - there's not a huge gain or THD variation over the 0.3mA to 0.4mA range, at least with this FET.

I've got some measurements with different FETs coming, we'll see what changes.

 

[OneRoomStudio]

ORS87 results​

As I like measuring stuff, I've built an "ORS87" testbench (originally in this thread) using the ORS87Plus PCB (here) designed by @Khron .

Initial measurements are without the feedback / frequency shaping network, for simplicity. Looks like this:


View attachment 135027
The circuit was run off a bench power supply (48V in series with 8k2, connected to S1-/S2+) and the output was taken from P+ (via an OPA1641 buffer, see earlier posts) to a mic input.

Input was connected to BP, via a 68pF capacitor. The FET Q1 and feedback cap C4 were socketed. D1 is 33V and R7 is 20K, as per the ORS87-Plus BOM.


There are lots of things to play with here, so let's start with C4 and biasing:

Open-loop gain​

Using the J113 FET, the chart below show the gain for a variety of drain currents (Id) and choices for C4:

View attachment 135028


The drain current is set by adjusting trimmer R7. It also sets the drain voltage Vd of the FET. We have Id = (V_D1 - Vd) / 57K, where V_D1 is the Zener voltage. In my build the zener measured as 33.6V, so we got the following:

Vd (V)	Id (mA)
22.2	0.20
19.4	0.25
16.5	0.30
13.7	0.35
10.8	0.40
8.0	0.45
5.1	0.50

Distortion​

Two charts here. The first shows distortion varying with Id, for a fixed input level (100mV RMS at 1KHz).

View attachment 135029

The second shows distortion varying with input signal level, when Id is tuned for lowest distortion at 100mV.

View attachment 135030

Opinions​

• Running without C4 isn't really an option, THD is very high without it, and it's asking a lot of the frequency-shaping network to provide corrective negative feedback. The network doesn't provide much feedback except at frequency extremes. I'll measure this later.
• The gain appears to be almost entirely dependent on the capacitances in the circuit, rather than the FET transconductance (which varies with Id, but is independent of C4).
• C4 = 10pF is probably OK for a 4:1 output transformer, and 5pF for a 7:1 or higher transformer, assuming you want around unity gain from capsule to mic output.
• Biasing is important but not super-sensitive - there's not a huge gain or THD variation over the 0.3mA to 0.4mA range, at least with this FET.

I've got some measurements with different FETs coming, we'll see what changes.

Seems like there might be some variables missing here.

1) In your circuit, the JFET is loaded by 1M. In the original, the transformer presents a dynamic load in the <20K range.
2) You're injecting signal directly into the "diaphragm" with a ground reference. In the actual circuit, the backplate connections (including the frequency-shaping network) are part of the capacitive loop that the signal develops in (as @Khron pointed out to me in another thread, your signal generator has to be in series with the capsule and back plate network, not in parallel).
3) You set the bias for lowest distortion at 100mV input, and then noted that the THD goes up as you add more signal....of course it does. You should be setting bias for lowest THD at something closer to 1V.
4) I don't know that I agree with the assertion that "Running without C4 isn't really an option." You're massively reducing the gain (by more than 10dB) for a difference of 1% THD. I don't understand the obsession with low THD in this circuit. If you want something with low THD, don't build a single-JFET, transformer-coupled mic. Go with an Alice or something like that. The whole point of building a "vintage U87-inspired" mic if FOR the THD and bandwidth restrictions.

Building a "colorful" mic circuit and then trying to make it as clean as possible strikes me as a very strange approach.

 

[Voyager10]

Seems like there might be some variables missing here.

1) In your circuit, the JFET is loaded by 1M. In the original, the transformer presents a dynamic load in the <20K range.

Good point. I didn't mention that I had a 47K load resistor in parallel with 1M R8 when making these measurements. The load is of course something else which affects the gain / distortion and it's worth testing the effect of different values here. 47K is roughly a 4:1 transformer into a 3K load (which is what I will end up with) or a 9:1 transformer into a 600R load (possibly closer to the original U87).

2) You're injecting signal directly into the "diaphragm" with a ground reference. In the actual circuit, the backplate connections (including the frequency-shaping network) are part of the capacitive loop that the signal develops in (as @Khron pointed out to me in another thread, your signal generator has to be in series with the capsule and back plate network, not in parallel).

Understood, but as I mentioned, this is just an initial look at the core FET amplifier stage. If we know the open-loop gain we can simulate the effect of the frequency-shaping network, so it's worth measuring this first.

I'm fully intending to build the complete circuit, including the 'calibration' input, and let you all know how it measures.

3) You set the bias for lowest distortion at 100mV input, and then noted that the THD goes up as you add more signal....of course it does. You should be setting bias for lowest THD at something closer to 1V.

At 100mV, the range of bias values for close-to-minimum distortion is quite wide, so I wondered whether the adjustment was more sensitive at higher voltages (i.e. the optimum range was narrower). I tried, and it wasn't, certainly with the J113: adjusting at a higher voltage gives no different end results.

Again, it's one of the many variables that can be measured and graphed (e.g. THD vs Id at 100mV, 200mV, 500mV ...) but there are only so many hours in the day.

4) I don't know that I agree with the assertion that "Running without C4 isn't really an option." You're massively reducing the gain (by more than 10dB) for a difference of 1% THD. I don't understand the obsession with low THD in this circuit. If you want something with low THD, don't build a single-JFET, transformer-coupled mic. Go with an Alice or something like that. The whole point of building a "vintage U87-inspired" mic if FOR the THD and bandwidth restrictions.

OK, whatever, but for myself I'm hoping to understand how close we can get to the published or known specs of the classic U87i, with a buildable modern circuit.

For instance, the U87i manual (on RecordingHacks) claims 0.5% THD at 122dB SPL. Doing the sums with a ~10mV/Pa capsule sensitivity gives 250mV in from the capsule at that point. The "C4=0" graphs look nowhere near that, so it is my considered opinion that it won't sound like a U87i either.

 

[abbey road d enfer]

Seems like there might be some variables missing here.

Indeed. Voyager 10 did not claim its work to be exhhaustive.

1) In your circuit, the JFET is loaded by 1M. In the original, the transformer presents a dynamic load in the <20K range.

The FET is actually loaded with less than 47kohms. Making it about 15kohm (47k//20k) would probably give scalable results.

2) You're injecting signal directly into the "diaphragm" with a ground reference. In the actual circuit, the backplate connections (including the frequency-shaping network) are part of the capacitive loop that the signal develops in (as @Khron pointed out to me in another thread, your signal generator has to be in series with the capsule and back plate network, not in parallel).

Although this is to take into account when evaluating the frequency response, in this particular case (evaluating THD vs. bias) it is irrelevant.

3) You set the bias for lowest distortion at 100mV input, and then noted that the THD goes up as you add more signal....of course it does.

Indeed.

You should be setting bias for lowest THD at something closer to 1V.

Why is 1V more relevant than 100mV? 100mV corresponds to about 104dBspl, why the need for 124dBspl?

4) I don't know that I agree with the assertion that "Running without C4 isn't really an option." You're massively reducing the gain (by more than 10dB) for a difference of 1% THD.

This shows you have a serious lack in metrology. Going from 2% to 0.3% is a 16dB improvement; it must not be taken as negligible.

I don't understand the obsession with low THD in this circuit. If you want something with low THD, don't build a single-JFET, transformer-coupled mic.

The quest for low THD starts with measuring it. This type of circuit is indeed capable of quite low distortion, and the Neumann engineers always endeavoured to produce the lowest possible THD. It is clearly documented.

Go with an Alice or something like that. The whole point of building a "vintage U87-inspired" mic if FOR the THD and bandwidth restrictions.

There are today several possibilities for building low THD high spl head amps that were not available to Neumann engineers of the 70's.

Building a "colorful" mic circuit and then trying to make it as clean as possible strikes me as a very strange approach.

You don't know (and I don't) Voyager10's intentions.
Personally, I think V10's work is to be encouraged.

 

[OneRoomStudio]

This shows you have a serious lack in metrology. Going from 2% to 0.3% is a 16dB improvement; it must not be taken as negligible.

My point was that with much lower circuit gain, your SNR will be worse, all to buy you ~1% less THD, which may or may not be an audible difference.

 

[abbey road d enfer]

My point was that with much lower circuit gain, your SNR will be worse, all to buy you ~1% less THD, which may or may not be an audible difference.

Buying 1% THD is meaningless.
Going from 10% to 9% is a meagre step. Going from 1.1% to 0.1% is a huge step.
The experiment conducted by V10 just concurs with common knowledge that for a single stage applying x dB of NFB results in the same improvement in THD.
Once you express THD in dB, it all makes sense.

 

[OneRoomStudio]

Buying 1% THD is meaningless.
Going from 10% to 9% is a meagre step. Going from 1.1% to 0.1% is a huge step.
The experiment conducted by V10 just concurs with common knowledge that for a single stage applying x dB of NFB results in the same improvement in THD.
Once you express THD in dB, it all makes sense.

Fair, but we’re only talking about a total of around 1%-2% THD before the improvement, which is barely audible. If we were going from 10% to 1% the exercise would make sense.