Embarrassingly basic PCB layout question: TO5-8 overlaid with DIP-8 okay?

[user 133392]

You might have a look at these:

https://www.cimarrontechnology.com/product/browndog-020601a-dip8-to-to99-adapter
https://www.cimarrontechnology.com/product/browndog-020601b-to99-to-dip8-adapter

 

[rock soderstrom]

I've been using EasyADA also - I got some PCBs last month that were really nice quality.

Standard or Pro edition? I am EasyEDA user, too. I am still using the standard edition.

 

[dmp]

Standard or Pro edition? I am EasyEDA user, too. I am still using the standard edition.

I've only been using the standard too

 

[dmp]

Soapfoot, here is a 500 series EQ I am working on. If this would help you out, pm your easyADA email and I'll share the project with you.

A few things that sped things up, you can import kicad files.
Here are some threads with kicad for 500 series (and a bunch of other helpful info)
https://groupdiy.com/threads/500-vpr-style-pcb-fabrication.81419/https://groupdiy.com/threads/500-card-edge-in-kicad.78216/page-2https://github.com/tormyvancool/kiCAD_Series500_Compatible_Template
I was able to load the 15pin connector from one of the kicad uploaded on GDIY and save the footprint to my library.
Then I got the board outline from the kicad zip on github.
I still need to check all this (print out 1:1 and make sure it lines up in the rack). And this project isn't nearly done - just getting going

 

[dmp]

How important is it to not have vias?
I've read they're bad, but some seem unavoidable when routing

 

[JohnRoberts]

How important is it to not have vias?

Back in the day there was a cost associated with vias, since it meant yet another drilled hole, these days AFAIK there is no marginal cost associated with it.

I've read they're bad, but some seem unavoidable when routing

Ideally it is easier to troubleshoot when you don't have lots of vias... even worse for troubleshooting are multi-layer boards where traces can hide in middle earth.

JR

 

[soapfoot]

Standard or Pro edition? I am EasyEDA user, too. I am still using the standard edition.

Standard edition for me

 

[user 133392]

How important is it to not have vias?
I've read they're bad, but some seem unavoidable when routing

At one point ExpressPCB had a maximum hole count which if exceeded had an extra cost. They changed that policy but the layout software still counts them.
If you submitted a perf board layout they might want to have a word with you regarding the number of holes.
I can't recall every having a bad via out of hundreds of boards and do find them unavoidable.

 

[dmp]

I guess at audio frequencies they aren't a problem. Cost isn't an issue anymore. That 500 series EQ above is priced at about $1.60 a board (min 5)
Will make it easier to design the PCBs

 

[dmp]

The 500 edge connector and board outline above is now a public project at EasyADA called API500_board
Use at your own risk - I haven't tested it yet.

 

[MidnightArrakis]

I totally understand!

I guess that snapshot was from Kicad? shrug....looks like it to me.

I seldom do PCB layouts anymore, but Kicad is what I use.

In Kicad,you can set "Design Rules" which establish spacings for things like traces and how close to the edge, etc. The PCB manufacturer has corresponding rules. See what the PC board fab says for their standards and then add "a mil or two" on the layout.

I ASSume you already corresponded the pin differences between DIP9 and TO5-8. That always seems to confused me! lol

I expect Midnight Arrakis will chime in here with a long reply and I'll bow out <g>.

Bri

[I expect Midnight Arrakis will chime in here with a long reply] -- I'm hurt!!! I guess all of my studies of "Journalism" has made me "overly verbose" in my technical explanations of things here in this forum. Perhaps I should concentrate more on the "Readers Digest" version of things, huh???

/

 

[MidnightArrakis]

A better way to do it might be to make a combined footprint for the opamp that has both footprints, connected in the footprint. I just tried this quickly and the attached image is what it looks like.

If you want to try this, click on the DIP part in your schematic, then open the footprint manager from the tools menu.
Search for your part's original footprint on the right side, then click on it. A green edit button will appear.
When you click edit, it will open the footprint in a new window, which you can now edit. You can move and create pads and create tracks. I added 8 pads in the circle and create tracks between them and the DIP pads. I turned off the solder mask on the right two pads by left clicking and going into the pad properties and making the 'solder mask expansion' = 0
I'm not sure if this should be zero or not - probably have to research that a bit.
After you finish making the footprint, save it into your workspace.
Then you can assign the footprint to parts in your schematic through the footprint manager.

[make a combined footprint for the opamp that has both footprints] -- While this is an excellent suggestion, there is "another way to skin the cat" and it is the methodology that I typically use when faced with this dilemma. However.....since I am unfamiliar with the features and functions possible with the typical -- FREE -- PCB-design CAD programs that are commonly used by users of this forum, I do not know if my suggested methodology is doable/feasible/workable with these programs. Anyway.....here goes.....

Instead of trying to "marry" two different PCB-footprints together as a "single" footprint, go ahead and create a "copper geometry" for each of the footprint pins. In this case, you will need to create 8 different "copper geometries", one for each pin. This is because the sizes, angles and shapes of each "copper geometry" will be different for each pin. Of course, while you are creating each of these individual "copper geometries", you will be keeping in mind what your DRC-clearances need to be and allow for the proper spacing for the "Solder-Mask" reliefs. Now, in case nobody on here knows this, PCB fabricators normally do not like to see anything less than 10-mils between solder-mask reliefs. This violation typically occurs on closely spaced IC pins and on connector pins.

So.....whatever size your "copper-geometry" ends up being, a good "rule-of-thumb" is to oversize your solder-mask by 10-mils. What you then need to do is to make certain that the actual solder-mask between pins is 10-mils or greater. If so, then you are "GOOD-TO-GO"!!! YAY!!!

Now.....within the more "industry-standard" PCB-design programs that I use, you have the option of placing the "Drill Hits" of a PCB-footprint at specific X/Y coordinates, relative to the PCB-footprints' origin. I do not know if this is available in the -- FREE -- programs that are typically used here. In any case.....once I would have generated all 8 of my "copper geometries" and made sure they all met my DRC-clearance checks, I would then place 2 "Drill Hits" within each "copper geometry" located at specific X/Y locations needed for each of the different packages. In this case, an 8-Pin DIP and a TO-5-8 package.

What all of this ends up doing is this.....you end up with only a -- single -- PCB-footprint, that really has only "8-Pins" as far as the schematic is concerned, but it also has 16 "Drill Hits" (which the schematic doesn't care about) as "2-sets of 8" in order to easily accommodate the two widely different and divergent device packages. So, this ends up being a "win-win" situation.

Now.....while all of this detailed information -- may -- sound wildly complicated.....I can assure you that it really isn't!!! Creating such a PCB-footprint within the PCB-design programs that I normally use would only take me a few minutes. Again, I have no idea if what I have just explained is "doable" within the -- FREE -- PCB-design programs that are used by the members here.

Brian -- I really did try to keep this explanation down to a minimum!!! But.....in order to fully explain things in enough detail to have them make sense, it sometimes "takes a lot of words" to fully describe the operation of something so someone else can easily follow along and then duplicate it for themselves!!! If you can describe to me what I could have left out of the above description while still keeping its context intact, let me know, OK???

OK.....Kids!!! This concludes today's class on "How To Create A PCB Footprint Out Of Copper-Geometries Using Multiple Drill Hits".

We now return you to your regularly scheduled forum comments!!!



/

 

[MidnightArrakis]

How important is it to not have vias?
I've read they're bad, but some seem unavoidable when routing

[How important is it to not have vias?] -- As Mr. John Roberts has mentioned.....it doesn't matter anymore how many vias your layout has. It -- USED -- to matter "back in the old days".....but, not anymore!!!

Prior to the whole COVID--19 scenario and nationwide lockdown, I was working at a large defense contractor as a "PCB Designer" and the PCB's that were being designed then had.....get ready!!!......get Ready!!!!.....GET READY!!!!!.....OVER ONE-MILLION VIAS on their circuit boards!!! YIPES!!!

So.....I certainly wouldn't worry about how many vias your layouts have these days!!! However.....make SURE that you only use as many vias as you NEED!!! Watch your routing and see if there are ways in which you can re-route one or more tracks and eliminate some vias, even if it means placing some routes on the "other" layer, contrary to how your board is being routed, OK???

/

 

[Brian Roth]

[I expect Midnight Arrakis will chime in here with a long reply] -- I'm hurt!!! I guess all of my studies of "Journalism" has made me "overly verbose" in my technical explanations of things here in this forum. Perhaps I should concentrate more on the "Readers Digest" version of things, huh???

/

I was just making a joke....which is why I added the <g> to indicate I was grinning. Didn't intend to be critical. Your comments are always instructive!

Bri

 

[MidnightArrakis]

I was just making a joke....which is why I added the <g> to indicate I was grinning. Didn't intend to be critical. Your comments are always instructive!

Bri

[I was just making a joke] -- I knew that!!! And.....my answer was a "joke" as well. I know you well enough from many other posts that you were just kidding!!! However, I figured that my - humor - was a bit too subtle to perhaps easily recognize it as such. Online humor can be a rather difficult emotion to convey, no???

Now.....I wonder if anyone on here has bothered to read my post, let alone digest and understand it, while also knowing how to apply what I have written about within their -- FREE -- PCB-design CAD-program? While the "technical space" between today's available -- FREE -- PCB-design programs and the various "industry-standard" PCB-design programs that costs several thousands of dollars is certainly narrowing, there are still several commands, features and functions within the "industry-standard" programs that have yet to trickle-down to the -- FREE -- program level.

> NOTE: If anyone reading my above previous post about "drill hits within copper geometries while creating a PCB-footprint" can't quite understand all of what was mentioned, just let me know, OK??? I'll try again to make things a bit more simpler to understand.

/

 

[jasonallenh]

Thanks! I’m using EasyEDA

I’m probably way less experienced with this kind of thing than the average user here

In that case, combine that into a new library and save it...so I can use it in EasyEDA later

 

[kingcredie]

I'm entirely self-taught so please forgive the super basic question.

If I wanted to be able to accommodate both a TO5-8 footprint and DIP-8 footprint, is this an okay strategy?

View attachment 106582

For all I know this is a super common thing to do--I've seen it done with through-hole DIP-8 and smaller SMT packages, but I can't recall ever having seen it done with DIP-8 and TO5-8. The only question is whether some of the pads might end up borderline too-close. Otherwise it seems it could work okay.

Any reason I shouldn't do this?

Thanks so much

Hi,

It is a very small board, right? Usually, the PCB factories will make as panel format.
Usually, the space between pads and the outline need 0.4mm at leasts.

Linda